Webinar: Automating the Integration Workflow with IP Centric Design

Online

(Work email required for verified registration) During a project, subsystem and full-chip integration plays a crucial role. Integration can be particularly challenging on large SoCs with distributed teams due to complexity of the integration process, multi-site infrastructure issues, as well as the need to collaborate across multiple time zones. Often, integrators must integrate design blocks …

CadenceCONNECT: Tech Days Europe 2024 – Dresden

Hilton Dresden Hotel An der Frauenkirche 5 D, Dresden, Germany

Date: Tuesday, May 14, 2024 Venue: Hilton Dresden Location: An der Frauenkirche 5, 01067 Dresden, Germany Parking: There is parking at the hotel with a charge of €28 per day. You will receive further information in your registration confirmation email. Analog, RF, and Mixed-Signal IC Design Learn how the latest developments within Virtuoso Studio and Spectre platforms can significantly …

Webinar: Speed Up Your Electronic Component Design with HPC

Online

Electronic components design and their integration on PCBs involve complex simulations to accurately predict EM fields and forces. These simulations can be computationally intensive and time-consuming. High-performance computing (HPC) capability built into Ansys Maxwell core technology significantly accelerates the electronic component design process, enabling quick iteration, optimization, and validation. Maxwell's ECAD capability allows modeling and …

DVClub India Meeting: Ensuring my Design Verification is ISO26262 Compliant

Online

Ensuring my Design Verification is ISO26262 Compliant With the widespread of the modern automobiles, run and regulated by automotive ECUs, the need for advanced safety features has also become inevitable. And this is why today modern vehicles are required to adhere to the safety standards listed within the Automotive Safety Integrity Level (ASIL). In this …

Webinar: Maximize Productivity with Deep Insights into PPA Trajectories

Online

The digital chip design flow carries with it an enormous wealth of untapped information regarding the health and status of your SoC design. The ability to efficiently mine this data provides chip designers with comprehensive visibility and actionable insights to uncover PPA opportunities. This webinar will introduce you to Synopsys Design.da, the industry’s first comprehensive data-visibility …

DVCon Japan 2024

Shinagawa, Tokyo, Japan Shinagawa, Tokyo, Japan

The Design & Verification Conference & Exhibition is the premier conference on the application of languages, tools, methodologies, and standards for the design and verification of electronic systems and integrated …