Join colleagues at the largest optical manufacturing conference and exhibition in North America SPIE Optifab is the premier event to meet with top companies and learn about the latest optical …
RISC-V is defining the future of open computing by providing unprecedented freedom to innovate. More than 13 billion RISC-V cores have shipped, powering new innovations in AI/ML, wireless, automotive, data …
Event Summary The year 2025 is both a turning point for integrated photonics as a key enabler for AI, physical and infrastructure interconnect, and the International Year of Quantum (IYQ). In our event, we are going to explore the enabling technologies shared by these two exciting fields. While these systems need to exist in a …
Continue reading "CadenceCONNECT: Photonics and Quantum Technologies"
Europe's Role & Chips Act 2.0 Priorities The European Union is currently developing a new version of the Chips Act program. The European Chips Act 2.0 represents a strategic initiative to strengthen the European semiconductor ecosystem. Building on the original Chips Act adopted in 2023, this updated framework aims to address emerging technologies such as …
*Work Email Required* Edge AI systems increasingly require on-chip integration of large-capacity memory, compute engines, and inference-optimized accelerators—all within strict power, latency, and footprint constraints. This webinar provides a an …
Continue reading "Webinar: IP Design Considerations for Real-Time Edge AI Systems"
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem …
Continue reading "2025 TSMC Open Innovation Platform Ecosystem Forum – Tokyo"
The 2025 International Conference on Computer-Aided Design Call For Papers Jointly sponsored by IEEE and ACM, IEEE ICCAD is the premier forum to explore new challenges, present leading-edge innovative solutions, …
The increasing demand for accelerated computing solutions calls for an agile hardware design methodology to be able to keep up with fast evolving landscape of algorithms. Traditional hardware design methodology …
CadenceCONNECT: Jasper User Group 2025 is October 29 and 30 in San Jose, CA. This interactive, in-depth technical conference connects designers, verification engineers, and engineering managers from around the world …
As digital chip design complexity grows, engineering teams face increasing pressure to meet aggressive PPA targets on tight schedules. To overcome this challenge, the EDA industry requires a revolutionary shift …
Description BLT, an AMD Premier Design Services Partner and Authorized Training Provider, presents this webinar. Unlock the potential of the AMD Kria SOM and discover Time-Sensitive Networking (TSN) benefits for …
October 29, 2025 - 11:00 AM EST October 30, 2025 – 10:00 AM JST/KST Discover the 5 Critical Memory Market Trends Reshaping Semiconductors in 2026 AI workloads, HBM4 adoption, and …
Continue reading "Webinar: 5 Expectations for the Memory Market in 2026"
