The International Conference for High Performance Computing, Networking, Storage, and Analysis HPC Ignites. St. Louis is the place to be this fall as the high performance computing community convenes for …
The Netherlands has been the home for Hardwear.io since 2015. We are very excited to host the industry from automotive, healthcare, semiconductor, IoT, industrial control systems and Govt/Defences Institutes to join us for Hardwear.io NL scheduled on 17th Nov to 21st Nov 2025 at Amsterdam Marriott Hotel Learn, share, build, collaborate with 100+ companies attending …
Continue reading "Hardwear.io Security Trainings and Conference Netherlands 2025"
The Component-based TPA and Virtual Prototyping Master Class is a 3-day live training event that brings together the NVH community at the NVH facility in Leuven, Belgium. This immersive program features theoretical …
Continue reading "MASTER CLASS: Component-based transfer path analysis and virtual prototyping"
SEMICON Europa 2025 is co-located with productronica and will take place in November 18-21, 2025 in Munich, Germany. This year’s theme Global Collaborations for European Economic Resilience expresses that global collaborations are not just beneficial for Europe's resilience, they are essential. In today's interconnected world, Europe cannot afford to operate in isolation. By working closely with other nations, …
Discover how the latest MEMS and imaging technologies are enabling next-level value creation across industries. Explore cutting-edge AI-enhanced sensing, data fusion, and their transformative impact on automotive, healthcare, and smart systems. Learn how these technologies are driving Europe's leadership in the sensor revolution while shaping a more intelligent, interconnected future. Join us in Sensing (R)evolution: …
Continue reading "Sensing (R)evolution: Sustaining Europe’s Leadership"
From Theory to Practice: Applying Timing Constraints Workshop Do you struggle to identify which constraints are needed for a design or how to properly input them? This workshop will cover how to use features in Vivado, clock domain crossing strategies, and how to get the most out of static timing analysis for Versal devices. This …
Continue reading "From Theory to Practice: Applying Timing Constraints Workshop"
Date: Nov. 20, 2025 Time: SIA Reception at 5:00 pm Dinner, Awards Presentations, & Keynote Remarks at 6:30 pm After-Dinner Reception at 8:30 pm Location: Signia by Hilton San Jose 170 S Market St San Jose, Calif.95113 PRIORITY SPONSORSHIP PERIOD NOW OPEN! The 2025 SIA Awards Dinner Priority Sponsorship Period is now open! Only Gold …
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation. As the AI …
Continue reading "2025 TSMC Open Innovation Platform Ecosystem Forum – Amsterdam"
Description Clock domain crossings (CDCs) are a critical aspect of FPGA and embedded system design, and handling them correctly is essential for reliable operation. In this one-hour webinar, we’ll break down CDC fundamentals, explore best practices for managing single-bit and bus CDCs, and demonstrate how to leverage Xilinx Parameterized Macros (XPM) for seamless synchronization. Join …
Continue reading "Webinar: Mastering Clock Domain Crossings (CDC) and Synchronization Techniques"
Speaker: Hong-Cheang Quek, AE Director 10:00am~11:00am iPegasus Verification System for Virtuoso Studio 11:00am~11:15am Q&A Description: Today's complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence …
Continue reading "CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio"
Join us for the 2025 TSMC OIP ECOSYSTEM FORUM Get ready for an electrifying dive into the future of semiconductor design at the 2025 TSMC Global Open Innovation Platform® (OIP) Ecosystem Forum! This isn’t just an event; it’s a dynamic hub where the brightest minds converge to ignite the next wave of innovation. As the AI …
Continue reading "2025 TSMC Open Innovation Platform Ecosystem Forum – China"
100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS Inside IEEE IEDM 2025 Focus Sessions Focus Session #1 - Efficient AI Solutions: Architecture, Circuit, and 3D Integration Innovations for …
Continue reading "IEDM 2025 – 71st Annual IEEE International Electron Devices Meeting"
Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …
Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. For example, today's application-specific ICs and microprocessors can contain upwards of 100 million transistors. Traditional testing relies on …
Semiconductor and integrated circuit developments continue to proceed at an incredible pace. The industry as a whole has gotten to this point of incredible complexity through the process of countless …
Failure and Yield Analysis is an increasingly difficult and complex process. Today, engineers are required to locate defects on complex integrated circuits. In many ways, this is akin to locating …
Continue reading "Semitracks Course: Failure and Yield Analysis"
Product reliability and qualification continues to evolve with the electronics industry. New electronics applications require new approaches to reliability and qualification. In the past, reliability meant discovering, characterizing and modeling …
Continue reading "Semitracks Course: Semiconductor Reliability and Product Qualification"
Electrical Overstress (EOS) and Electrostatic Discharge (ESD) account for most of the field failures observed in the electronics industry. Although EOS and ESD damage can at times look quite similar …
Continue reading "Semitracks Course: EOS, ESD and How to Differentiate"
