IEDM 2025 – 71st Annual IEEE International Electron Devices Meeting

100 YEARS of FETs: SHAPING the FUTURE of DEVICE INNOVATIONS Inside IEEE IEDM 2025 Focus Sessions Focus Session #1 - Efficient AI Solutions: Architecture, Circuit, and 3D Integration Innovations for Memory and Logic Focus Session #2 - Beyond Silicon: The Invisible Revolution in Thin-Film Transistors Focus Session #3 - From P-bits to Qubits: Classical, Quantum-Inspired …

CadenceTECHTALK: Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure

Speaker: Kee Tat Ong, Principal Application Engineer 10:00am~11:00am Quantus Insight: Intelligent Parasitic Debugging, Optimization, and Signoff Closure 11:00am~11:15am Q&A Description: With more designs migrating to advanced process nodes, chips are getting smaller, but design complexity is increasing in order to deliver better power, performance, or area. These optimizations are restricted by the time window to …

Essential Debugging Techniques Workshop

Essential Debugging Techniques Workshop This workshop is for hardware engineers, system architects, and anyone who wants to learn best practices for debugging challenging issues encountered while developing FPGAs, SoCs, PCBs, and embedded systems using the Vivado Design Suite. The features and capabilities of the Vivado Integrated Logic Analyzer are covered in lectures and demonstrations, along with …