Webinar: Why AI-Assisted Security Verification For Chip Design is So Important

It is well-known that AI is everywhere, and the incredible power of this new technology is enabled by highly complex, purpose-built silicon. But there is a silent enemy of this substantial, world-changing progress. Something that has the power to steal a bright future from all of us. The hardware root of trust for those advanced custom chips is at the epicenter of the story. Simply put, AI advances have made the hardware root of trust vulnerable to attack. You can see the stories in news headlines. And it’s getting worse.

Thankfully, there are companies focused on this problem. Caspia Technologies is a bright spot among those companies. It is developing an AI platform of tools, a methodology and training to fortify chip design practices against this threat to secure future innovation. The company presented an important webinar on this topic recently. If you’re involved in advanced chip design, you need to see this webinar. A replay link is coming. Let’s first look at some details about why AI-assisted security verification for chip design is so important.

Who’s Presenting

The webinar contains three parts – an overview of the problem and Caspia’s solution, a live demonstration of how to find and fix security flaws in real chip designs and an interactive Q&A session with the webinar audience. There are two well-qualified members of the Caspia team presenting:

Beau Bakken first provides an overview of security risks all design teams face today. He then describes an effective strategy to minimize these risks and illustrates how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies. Beau has been with Caspia for over five years. Before that, he spent time at the National Science Foundation.

Dr. Paul Calzada then presents a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identification of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions. Paul holds a PhD in Computer Engineering from the University of Florida.

What Is Covered

Beau begins the webinar with some eye-opening information regarding the growing vulnerability of the hardware root of trust and its associated firmware and microcode. He shares alarming trends regarding the growth of hardware-focused attacks and presents some real examples of the problem taken from news headlines. 

Beau then explains how AI is making it easier to attack the same hardware that is accelerating AI workloads. He points out that AI is the problem and the solution to this dilemma. He explains that hardware is NOT patchable, and chip security flaws will cost billions of dollars to recall and repair. Security flaws are simply not an option any longer.

Beau then explains the architecture of Caspia’s secure-by-design approach to addressing this important issue. He explains how Caspia’s tools easily integrate into existing design flows, how these tools find security flaws and assist in removing them early in the design process, before a disaster occurs in the field.

Since AI is causing the problem, the solution must also use AI to see what’s coming and remove the threats. Beau also describes Caspia’s generative and agentic technology that makes every designer a security expert.

Paul then demonstrates how to find and fix security flaws in a real open-source design. He uses Caspia’s CODAx static security verification tool to do this. You learn the depth of security checks that CODAx performs so subtle security weaknesses can be found and fixed early.

Watch the Webinar Replay Now!

If you are designing advanced chips that will be part of AI workload acceleration, this is a must-see event. Watch the replay now, you’ll be glad you did.  Here is a link to watch the replay. And that’s how you can find out why AI-assisted security verification for chip design is so important.

Also Read:

A Six-Minute Journey to Secure Chip Design with Caspia

Large Language Models: A New Frontier for SoC Security on DACtv

Caspia Focuses Security Requirements at DAC