How Sarcina Revolutionizes Advanced Packaging #61DAC

#61DAC was buzzing with discussion of chiplet-based, heterogeneous design.  This new design approach opens new opportunities for applications such as AI, autonomous driving and even quantum computing. A critical enabler for all this to work is reliable, cost-effective advanced packaging, and that is the topic of this post. Sarcina Technology is a company focused on delivering reliable, cost-effective advanced packaging through a palette of advanced engineering services. You can learn more about this unique company on SemiWiki here. Let’s see how Sarcina revolutionizes advanced packaging at #61DAC.

The Keysight Connection

As DAC becomes the chips to systems conference, Keysight Technologies becomes more relevant at the show. In its own words, Keysight is your innovation partner, delivering market-leading design, emulation, and test environments that help you develop and deploy faster, with less risk, throughout the product life cycle. Keysight had a partner theater in its booth at #61DAC, and Sarcina’s CEO, Larry Zu was there to explain how Sarcina revolutionizes advanced packaging with Keysight’s help.

The focus of Larry’s presentation was around something called Bump Pitch Transformer package design. A Bump Pitch Transformer for high I/O interconnect density between adjacent dice is a silicon bridge technology that replaces expensive silicon TSV interposers with more cost-effective re-distribution layers (RDL).  It’s ideal for homogenous and heterogenous chiplet integration targeting high-performance computing (HPC) devices for AI, data center, microprocessor, and networking applications.  

Larry explained that Fan-Out Chip-on-Substrate with Silicon Bridge (FOCoS-B) is the latest Bump Pitch Transformer technology. Armed with production-level package design rules and the know-how to design advanced FOCoS-B package with this technology, today Sarcina Technology is ready to design this package for any customers in the world.  The manufacture  is now available through OSAT companies such as ASE and SPIL, breaking a logjam of innovation created by previous proprietary technologies and essentially democratizing the 2.5D era. The technology transforms silicon micro-bump pitch (~45 microns) to C4 bump pitch (130-150 microns).

Sarcina Technology provides a choice of either silicon bridge (graphic 1a) or chip-last technology (graphic 1b) depending on I/O interconnect density between adjacent dice. FOCoS-B is suitable for higher density and FOCoS-CL (Chip Last) is suitable for lower density.  See figure below.

While all these advances are exciting, Larry pointed out the complexities design teams will face to reliably and accurately achieve the goal. Challenges include:

• Shrinking bump pitch to increase interconnect density
• Homogeneous & heterogeneous chiplet integration
• Die-to-die interconnection, communication, & protocol standardization
• Bump pitch transformer from microbump pitch to C4 bump pitch
• Fab or assembly house availability
• Design expertise and factory engineering collaboration
• Cost effective EDA tools
• Bump pitch transformer (interposer) yield and its assembly yield
• Cost effective testing

Getting all these right requires substantial engineering talent and a highly accurate simulation and analysis tool flow. This is where Keysight’s PathWave Advanced Design System (ADS) and Memory Designer help quite a bit. Larry explained that the results of these tools have been tuned to be highly accurate. If the simulations look good, one can tape out with confidence.

The Bump Pitch Transformer (BPT) services offered by Sarcina include:

• BPT (interposer) design, O/S test pattern insertion, fabrication & BPT wafer sort
• PKG substrate design, PI/SI + thermal system simulation, & substrate fabrication
• Package assembly, final test, and production services

Larry also reviewed the substantial experience and accomplishments the Sarcina team has in this area.  These include:

• Successfully designed, fabricated, & tested a 2.5D Si interposer package
• Si interposer design, O/S test pattern insertion, fab, & interposer wafer sort
• Package substrate design, PI/SI, thermal simulation, & substrate fabrication
• Assembly, final test, and production services
• 47.5 mm x 47.5 mm HFCBGA with 2019 BGA balls
• 1 ASIC + 2 HBMs on a silicon interposer
• 12 substrate layers
• 320 Watts
• 32 lanes of 25 Gbps SerDes
• 16 lanes of 16 Gbps PCIe-4 

To Learn More

A comprehensive case study is available from Keysight that discusses how Sarcina Delivers Right-First- Time Packages Using ADS For Chip-Package-Board Simulation. You can get a broad overview of Sarcina’s services here.  And you can learn more about advanced packaging here. And that’s how Sarcina revolutionizes advanced packaging.