Webinar: Why AI-Assisted Security Verification For Chip Design is So Important

In this webinar, we will explore the growing threat that AI-fueled cyberattacks pose to chip designs and how to add expert-level security verification to your design flow to minimize those risks.

We will expose some of the details of the existential risk for electronic systems with real examples. We will then describe technology that easily integrates with your existing design flow to find and fix securty weaknesses before tapeout.

We will show you how these tools work on real designs as well.

WHO SHOULD ATTEND THIS WEBINAR?

If you are designing chips to deploy in networked environments, you need to understand the risks ahead and how to minimize them.

If you are procuring chips you also need to understand the risks ahead so you can ensure your chip supplier is taking effective precautions.

SPEAKERS

Beau Bakken will provide an overview of security risks all design teams face today. He will then describe an effective strategy to minimze these risks and illustrate how it works. Beau is VP of Products at Caspia. He works on the definition of new products and the associated go to market strategies

Dr. Paul Calzada will take you through a live demonstration of CODAx, Caspia’s security-aware static verification solution. You will see the analysis of a real design and the identifcation of security weaknesses. Paul is an R&D Application Engineer at Caspia. He works with customers to ensure effective deployment of Caspia’s solutions.

* This webinar is in partnership with SemiWiki and Caspia Technologies

REGISTER HERE