DVCON U.S. 2026
DVCon is the premier conference on the application of languages, tools, and methodologies for the design and verification of electronic systems and integrated circuits. The focus of the conference is the usage of specialized design and verification languages such as SystemVerilog, Verilog, VHDL, PSS, SystemC and e, as well as general purpose languages such as C, C++, Python, PERL and Tcl. Tools and methodologies include the use of artificial intelligence, machine learning, open-source software, hardware and architecture, testbench automation, hardware-assisted verification, hardware/software co-verification, formal verification, functional safety and security, transaction-level system design, high level synthesis, low power design techniques, 3D chip designs, IP-based SoC design methods, reference flows and Mixed Signal design and verification.
Call for Submissions
The deadline to submit your proposal for an extended abstract, sponsored tutorial, or sponsored workshop is fast approaching! Be sure to get your submission in by September 7.
The Design & Verification Conference is looking for submissions for the in-person 2026 Conference and Exhibition. This conference focuses on the practical aspects of design and verification of electronic systems and integrated circuits. This could be applications of languages, tools, methodologies, and/or standards. This could be your chance to help the industry we are all a part of. For those familiar with DVCon, the submission timeline has changed for this year. Please see below for more details.
DVCon honors the Sutherland Best Paper submissions. The awards will be selected by the attendees at DVCon, based on the quality of both the paper and their presentation. Awards will be offered for both lecture and poster presentation formats. So please submit your abstract and join DVCon U.S. 2026!
Intel’s Pearl Harbor Moment