CadenceTECHTALK: Reduce SMT Parasitic Design Failures with Innovative Filter Topologies

Join our webinar to discover challenges and optimization strategies for designing reliable and efficient filters using SMT capacitors and inductors. A lumped prototype is monotonic in the stopbands, while an SMT filter may have spurious responses, which can be affected by topology changes and capacitor placement. Additionally, simple S-parameter representations do not account for variations in parasitic behavior due to substrate thickness, dielectric constant, and solder pad dimensions. Ultimately, PCB layout parasitics can lead to significant differences between simulations based on lumped prototype values and final measured results based on actual SMT component values, leading to potential product delays and/or system failure.

Learn how to manage and modify spurious performances effectively through innovative SMT filter topologies. Gain insights into how PCB layout contributes to parasitic behaviors that affect your SMT component values. Understand how to enhance your design’s performance with Cadence’s Microwave Office software and highly accurate Modelithics simulation models, ensuring your designs are right the first time.