CadenceTECHTALK: iPegasus Verification System for Virtuoso Studio

Speaker: Hong-Cheang Quek, AE Director

10:00am~11:00am iPegasus Verification System for Virtuoso Studio

11:00am~11:15am Q&A

Description: Today’s complex SoC designs significantly increase layout creation and verification time, especially at advanced nodes. To meet overall demand for faster design cycle turnaround time, bridge a demand gap, and improve productivity between custom implementation and physical verification tools, Cadence iPegasus Verification System delivers instant signoff quality design rule checks (DRC) to achieve higher quality layout from the Virtuoso Layout Suite. In addition to performing DRC/density checks using foundry-certified signoff rule decks, iPegasus is also generate metal fills using foundry-provided fill decks. Join this presentation to learn how iPegasus can boost your productivity and be easily adopted as part of your daily work.

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