Key Takeaways
- Siemens EDA's AI Workflow System enhances the EDA ecosystem by integrating knowledge capture, next-gen debug platforms, and automated fixing to optimize Design Rule Checking (DRC) sign-off.
- The Siemens EDA AI System is an open platform that utilizes LLMs and ML models to provide intelligent solutions across tools like Calibre, Aprisa, and Solido, ensuring data security while accelerating workflows.
- Calibre Vision AI significantly speeds up debugging processes, enabling early issue identification and cross-team collaboration, exemplified by AMD's experience in reducing root-cause analysis time.
In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence is revolutionizing this process. Delivered by David Abercrombie, Sr. Director of Calibre Product Management at Siemens EDA, alongside AMD experts Stafford Yu and GuoQin Low, the talk highlights collaborative advancements with TSMC and AMD to enhance productivity across understanding, fixing, debugging, and collaboration in DRC sign-off.
The presentation opens with an overview of Siemens EDA’s new AI Workflow System, designed to boost the entire EDA ecosystem. This system integrates knowledge capture, next-gen debug platforms, AI debug assistance, and automated fixing, ultimately optimizing DRC sign-off. Central to this is the Siemens EDA AI System, an open, secure platform deployable on-premises or in the cloud. It features a GenAI interface, a knowledge base, and a data lake that amalgamates Siemens EDA data, Calibre-specific data, and customer inputs. Powered by LLMs, ML models, and data query APIs, it enables intelligent solutions across tools like Calibre, Aprisa, and Solido. Key benefits include a single installation process, flexibility for customer integrations, and support for assistants, reasoners, and agents. This infrastructure ensures AI tools are hosted on customer hardware, maintaining data security while accelerating workflows.
A major focus is on boosting user understanding through AI Docs Assistant and Calibre RVE Check Assist. The AI Docs Assistant allows users to query Siemens EDA tool documentation via browser or integrated GUIs, providing instant answers with RAG-generated citations. It supports specific tools and versions, includes company documentation, and collects feedback for continuous improvement. Integrated with Calibre’s Results Viewing Environment (RVE) and Vision AI, it streamlines access to knowledge. Complementing this, Calibre RVE Check Assist leverages TSMC’s Design Rule Manual (DRM) data, embedding precise rule descriptions and specialized images directly into the RVE. This enhances designers’ comprehension of rule checks, improving debugging experiences and productivity. Additionally, RVE Check Assist User Notes facilitate in-house knowledge sharing: designers capture fixing suggestions and images in RVE, storing them in a central database within the EDA AI Datalake. This shared repository allows organization-wide review, enhancing DRC-fixing flows by leveraging collective expertise.
Shifting to automated fixing, the presentation details Calibre DesignEnhancer, an analysis-based tool for sign-off DRC-clean modifications on post-routed designs. It includes modules like DE Via, which maximizes via insertion to reduce IR drop and boost robustness, and DE Pge, which enhances power grids by adding Calibre nmDRC-clean interconnects for better EM and IR performance. The engine supports LEF/DEF formats and outputs incremental, full, or ECO DEF files, integrating seamlessly with Place-and-Route tools. Its infrastructure handles simple and complex metal rules, such as spacing (M.S., V#.S.), enclosure (M.EN., V.EN.), and forbidden patterns (EFP.M., EFP.V.), considering connectivity and rule dependencies. Examples illustrate fixes like expanding or trimming edges to resolve end-to-end spacing violations, demonstrating its precision in layout contexts.
For debugging, Calibre Vision AI addresses full-chip integration challenges, such as handling billions of violations with sluggish navigation and limited perspectives. It enables “shift left” strategies, identifying issues early for Calibre-clean resolutions. Features include intelligent debug via check grouping (e.g., bad via arrays or fill overlaps), full-chip analysis at 20x speed (reducing 71GB databases to 1.4GB with instant loading), and cross-team collaboration through bookmarks, ASCII RDB exports, and HTML reports. Integration with the Siemens EDA AI System adds natural language capabilities for tool operations, data reasoning, and knowledge access.
AMD’s testimonial underscores real-world impact: on a design with 600 million errors across 3400 checks, Vision AI grouped them into 381 signals, enabling 2x faster root-cause analysis. Heatmaps revealed systematic issues like fill overlaps with clock cells or missing CM0 in breaker cells, compressing cycle times.
Bottom line: This collaboration between Siemens EDA, TSMC, and AMD exemplifies AI’s transformative role in DRC. By boosting workflows, understanding, fixing, debugging, and collaboration, these tools promise significant productivity gains, potentially shortening design cycles and improving chip reliability. As semiconductor nodes advance, such innovations are essential for maintaining competitive edges in high-stakes industries.
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