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Get Ready for a Shakeout in Edge NPUs

Get Ready for a Shakeout in Edge NPUs
by Bernard Murphy on 11-20-2024 at 6:00 am

trackstar in a race min (1)

When the potential for AI at the edge first fired our imagination, semiconductor designers recognized that performance (and low power) required an accelerator and many decided to build their own. Requirements weren’t too complicated, commercial alternatives were limited and who wanted to add another royalty to further reduce… Read More


Tier1 Eye on Expanding Role in Automotive AI

Tier1 Eye on Expanding Role in Automotive AI
by Bernard Murphy on 11-13-2024 at 6:00 am

Car EE system

The unsettled realities of modern automotive markets (BEV/HEV, ADAS/AD, radical views on how to make money) don’t only affect automakers. These disruptions also ripple down the supply chain prompting a game of musical chairs, each supplier aiming to maximize their chances of still having a chair (and a bigger chair) when the … Read More


Podcast EP260: How Ceva Enables a Broad Range of Smart Edge Applications with Chad Lucien

Podcast EP260: How Ceva Enables a Broad Range of Smart Edge Applications with Chad Lucien
by Daniel Nenni on 11-08-2024 at 10:00 am

Dan is joined by Chad Lucien, vice president and general manager of Ceva’s Sensing and Audio Business Unit. Previously he was president of Hillcrest Labs, a sensor fusion software and systems company, which was acquired by Ceva in July 2019. He brings nearly 25 years of experience having held a wide range of roles with software, … Read More


Changing RISC-V Verification Requirements, Standardization, Infrastructure

Changing RISC-V Verification Requirements, Standardization, Infrastructure
by Daniel Nenni on 11-07-2024 at 10:00 am

Abstract,Futuristic,Infographic,With,Visual,Data,Complexity,,,Represent,Big

A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

In Part Two, moderator Ron Wilson and Contributing Editor … Read More


Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution

Semidynamics: A Single-Software-Stack, Configurable and Customizable RISC-V Solution
by Kalar Rajendiran on 11-07-2024 at 6:00 am

Risc V CPU

Founded with a vision to create transformative, customizable IP solutions, Semidynamics has emerged as a significant player in the AI hardware industry. Initially operating as a design engineering company, Semidynamics spent its early years exploring various pathways before pivoting to develop proprietary intellectual… Read More


Arteris Empowering Advances in Inference Accelerators

Arteris Empowering Advances in Inference Accelerators
by Bernard Murphy on 11-06-2024 at 6:00 am

NoC Tiling min

Systolic arrays, with their ability to highly parallelize matrix operations, are at the heart of many modern AI accelerators. Their regular structure is ideally suited to matrix/matrix multiplication, a repetitive sequence of row-by-column multiply-accumulate operations. But that regular structure is less than ideal … Read More


MIPI solutions for driving dual-display foldable devices

MIPI solutions for driving dual-display foldable devices
by Don Dingee on 11-04-2024 at 10:00 am

H3 FPGA with MIPI for driving dual display folding devices

Flexible LCD technology has spurred a wave of creativity in device design, including a new class of foldable phones and an update to the venerable flip phone. Besides the primary display inside the fold – sometimes taking the entire inside area – a smaller secondary display is often found outside the fold. Introducing the secondary… Read More


Notes from DVCon Europe 2024

Notes from DVCon Europe 2024
by Jakob Engblom on 11-04-2024 at 6:00 am

semiwiki 1 dvcon europe 2024 cookie

The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.

Keynotes:

Read More

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro

Datacenter Chipmaker Achieves Power Reduction With proteanTecs AVS Pro
by Kalar Rajendiran on 10-30-2024 at 10:00 am

Alphawave Using proTeanTechs

As semiconductor technology advances and nodes continue to shrink, designers are faced with increasing challenges related to device complexity, power consumption, and reliability. The delicate balance between high performance, low power usage, and long-term reliability is more critical than ever. This growing demand … Read More


Podcast EP256: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale

Podcast EP256: How NoC Tiling Capability is Changing the Game for AI Development with Andy Nightingale
by Daniel Nenni on 10-29-2024 at 8:00 am

Dan is joined by Andy Nightingale, VP of product management and marketing at Arteris. Andy has over 37 years of experience in the high-tech industry, including 23 years in various engineering and product management positions at Arm.

Dan explores with Andy the significance of the recently announced tiling capabilities and extended… Read More