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WEBINAR: Elevate Your Analog Layout Design to New Heights

WEBINAR: Elevate Your Analog Layout Design to New Heights
by Daniel Payne on 11-26-2024 at 10:00 am

learning analog ic layout min

Analog IC layout is a demanding endeavor as it entails conforming to complex layout design rules, interpreting design intentions from the schematics and understanding arcane topics like transistor matching, noise tolerance, parasitics and latch up. These skills are often handed down from one generation to the next, one on … Read More


Silicon Creations is Fueling Next Generation Chips

Silicon Creations is Fueling Next Generation Chips
by Mike Gianfagna on 11-21-2024 at 6:00 am

Silicon Creations is Fueling Next Generation Chips

Next generation semiconductor design puts new stress on traditionally low-key parts of the design process. One example is packaging, which used to be the clean-up spot at the end of the design. Thanks to chiplet-based design, package engineers are now rock stars. Analog design is another one of those disciplines.

Not long ago,… Read More


I will see you at the Substrate Vision Summit in Santa Clara

I will see you at the Substrate Vision Summit in Santa Clara
by Daniel Nenni on 11-20-2024 at 10:00 am

Soitec Substrate Vision Summit

WIth packaging being one of the top sources of traffic on SemiWiki, I am expecting a big crowd at this event. A semiconductor substrate is a foundational material used in the fabrication of semiconductor devices. Substrates are a critical part of the manufacturing process and directly affect the performance, reliability, and… Read More


Alchip is Paving the Way to Future 3D Design Innovation

Alchip is Paving the Way to Future 3D Design Innovation
by Mike Gianfagna on 11-19-2024 at 6:00 am

Alchip is Paving the Way to Future 3D Design Innovation

At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains… Read More


Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
by Mike Gianfagna on 11-14-2024 at 6:00 am

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively… Read More


Changing RISC-V Verification Requirements, Standardization, Infrastructure

Changing RISC-V Verification Requirements, Standardization, Infrastructure
by Daniel Nenni on 11-07-2024 at 10:00 am

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A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.

In Part Two, moderator Ron Wilson and Contributing Editor … Read More


Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters

Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
by Daniel Nenni on 11-06-2024 at 10:00 am

banner for webinar

The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More


Notes from DVCon Europe 2024

Notes from DVCon Europe 2024
by Jakob Engblom on 11-04-2024 at 6:00 am

semiwiki 1 dvcon europe 2024 cookie

The 2024 DVCon (Design and Verification) Europe conference took place on October 15 and 16, in its traditional location at the Holiday Inn Munich City Centre. Artificial intelligence and software were prominent topics, along with the traditional DVCon topics like virtual platforms, RTL verification, and validation.

Keynotes:

Read More

Shaping Tomorrow’s Semiconductor Technology IEDM 2024

Shaping Tomorrow’s Semiconductor Technology IEDM 2024
by Scotten Jones on 10-23-2024 at 6:00 am

IEDM 2024 SFO

Anyone who has read my articles about IEDM in the past know I consider it a premiere conference covering developments of leading-edge semiconductor process technology. The 2024 conference will take place in San Francisco from December 7th through 11th.

Some highlight of this year’s technical program are:

AI  – Lots of artificial… Read More


Webinar: When Failure in Silicon Is Not an Option

Webinar: When Failure in Silicon Is Not an Option
by Daniel Nenni on 10-10-2024 at 6:00 am

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If the thought of a silicon respin keeps you awake at night, you’re not alone. Re-fabricating a chip can cost tens of millions of dollars. An unplanned respin also risks a delay in getting a product to market, which adds tremendous costs in terms of lost business.

Undoubtedly, adding to your sleep loss is the recent rise in respins.… Read More