IMGTC Webinar SemiWIki
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Designing chips for the AI era: what TSMC’s roadmap means

Designing chips for the AI era: what TSMC’s roadmap means
by Daniel Nenni on 09-25-2026 at 8:00 am

TSMC LC Lu OIP Event

About twenty years ago I worked with Cliff Hou, LC Lu, and the TSMC PDK team on reference flows with emerging EDA and IP companies. This was the precursor to the OIP. Having a person with LC Lu’s depth of R&D experience running the TSMC Design & Technology Platform is truly an honor, absolutely.

AI is creating two related… Read More


Tokens Per Watt Over Peak Performance: Retrofitting Heterogeneous Silicon for Production Inference

Tokens Per Watt Over Peak Performance: Retrofitting Heterogeneous Silicon for Production Inference
by Kalar Rajendiran on 09-24-2026 at 2:00 pm

Image for Article 2 SemiWiki Tokens per Watt or per Dollar

👉 This is Part 2 of an editorial series on the evolving economics of AI inference. If you missed Part 1, where I broke down the shift toward full-system integration, the lessons from the AI Infra Summit, and the “no forks” open-source philosophy, you can read it HERE: Beyond the Accelerator: Why Silicon Challengers … Read More


From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters

From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters
by Daniel Nenni on 09-24-2026 at 8:00 am

From Custom Silicon to AI Systems Why Cross Layer Engineering Matters

The central argument of Ankur Gupta’s AI Infra Summit keynote is simple but consequential: the next leap in AI infrastructure will not come from improving chips, servers, cooling systems, or data centers independently. It will come from optimizing the connections among them. Siemens frames this as a journey “from custom silicon… Read More


SEMICON West’s “Bridging design and Manufacturing with AI” Design Session Explores AI as Practical Lever Across Entire Lifecycle

SEMICON West’s “Bridging design and Manufacturing with AI” Design Session Explores AI as Practical Lever Across Entire Lifecycle
by Admin on 09-23-2026 at 10:00 am

Bridging sign and Manufacturing with AI

By Julie Rogers, Executive Director, Electronic System Design Alliance

2026 is “Bridging Design and Manufacturing with AI” during a day-long session Tuesday, October 13, from 10:30 a.m. to 4:30 p.m. at San Francisco’s Moscone Center, North Hall, Lower Level, Room 20.

The Design Session hosted and organized by the Electronic… Read More


Agentic AI Is Reshaping Semiconductor Design

Agentic AI Is Reshaping Semiconductor Design
by Daniel Nenni on 09-21-2026 at 10:00 am

ChipAgents DAC2026

Artificial intelligence is moving rapidly from an experimental aid to a foundational part of semiconductor engineering. In a recent industry talk, leaders from ChipAgents and Analog Devices described how agentic AI could help chipmakers manage soaring design complexity, accelerate product development, and improve the … Read More


TSMC’s 2026 OIP Forum to Spotlight the Technologies Shaping the Next Era of Chips

TSMC’s 2026 OIP Forum to Spotlight the Technologies Shaping the Next Era of Chips
by Daniel Nenni on 09-11-2026 at 6:00 am

TSMC OIP 2026

It’s that time of year again. Time certainly flies when AI is chasing you! This year marks the 18th TSMC OIP Ecosystem Forum, and it promises to be bigger and better than ever. My SemiWiki partners, Mike Gianfagna and Kalar Rajendiran, will join me in covering the event live, so stay tuned for all the news that’s fit to print.

Mike and… Read More


Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success
by Mike Gianfagna on 09-10-2026 at 2:00 pm

Webinar – Avestra Explains How to Achieve Assertion Driven Silicon Success

Studies have shown that nearly 20% of the verification cycle is spent on assertion generation, debugging, and methodology integration. This work remains largely manual today or is delegated to general-purpose LLMs that can produce incorrect assertions more than 30% of the time. Avestra attacks this problem with agentic AI … Read More


PDF Solutions CONNECT 2026: Where Semiconductor Data Meets AI

PDF Solutions CONNECT 2026: Where Semiconductor Data Meets AI
by Daniel Nenni on 09-10-2026 at 10:00 am

CONNECT 400x400

The semiconductor industry is entering a period in which manufacturing leadership will depend not simply on producing more data, but on turning that data into timely, trustworthy decisions. PDF Solutions CONNECT 2026 is designed around this challenge. Taking place October 15–16 at the Westin St. Francis in San Francisco, the… Read More


Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI
by Mike Gianfagna on 09-10-2026 at 6:00 am

Webinar – ChipAgents Shows You How to Break the Timing Closure Bottleneck with AI

We all know timing closure is one of the most challenging processes in chip design. Extracting actionable insight from massive timing reports, tracing violations back to RTL, and selecting the right fix across complex PPA tradeoffs all require deep expertise. And every change can trigger hours or days of tool runs and cross-team… Read More


Jalapeño Hot Chip, Cool Power Bill: OpenAI Turns Up the Heat on AI Inference

Jalapeño Hot Chip, Cool Power Bill: OpenAI Turns Up the Heat on AI Inference
by Daniel Nenni on 09-09-2026 at 2:00 pm

Jalapeño Hot Chip

OpenAI’s Jalapeño is a custom accelerator designed specifically for AI inference, particularly the low-latency, multi-chip workloads behind interactive and agentic systems. Its central idea is that useful performance cannot be reduced to peak floating-point operations or memory bandwidth. What matters is how quickly … Read More