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In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.
Patterson began with humor, noting… Read More
In a engaging presentation at a recent RISC-V summit, Martin Dixon, Google’s Director of Data Center Performance Engineering, took the audience on a metaphorical “road trip” to explore the company’s vision for integrating RISC-V into its massive warehouse-scale computing infrastructure. Drawing… Read More
In a compelling keynote at the RISC-V Summit North America 2025, Jeremy Dahan from AWS explored the challenges of embedded systems development and how cloud technologies can bridge the gap between local hardware tinkering and scalable, shareable environments. Drawing from his experience as an engineer, Dahan highlighted … Read More
Building a complex SoC is a risky endeavor that demands careful planning, strategic decisions, and collaboration across hardware and software domains. As highlighted in Darren Jones’ RISC-V Summit presentation from Andes Technology, titled “From Blueprint to Reality: Navigating SoC Tradeoffs, IP, and Ecosystem,”… Read More
Electrical rule checking (ERC) is a standard part of any design flow. There is a hidden problem with the traditional approach, however. As designs grow in complexity, whether full-custom analog, mixed-signal, or advanced-node digital, the limitations of traditional ERC tools are becoming more problematic. This can lead to… Read More
By Andy Nightingale, VP of Product Management and Marketing
As AI adoption accelerates across markets, including automotive ADAS, large-scale compute, multimedia, and edge intelligence, the foundations of system-on-chip (SoC) designs are being pushed harder than ever. Modern AI engines generate tightly coordinated, … Read More
In the rapidly evolving semiconductor industry, Design Rule Checking (DRC) remains a critical bottleneck in chip design workflows. Siemens EDA’s presentation at the 2025 TSMC Open Innovation Platform Forum, titled “AI-Driven DRC Productivity Optimization,” showcases how artificial intelligence … Read More
Tarun Verma, Managing Partner of Silicon Catalyst, delivered a keynote at Verification Futures Austin titled “Revitalizing Semiconductor StartUps.” Drawing from his role in the world’s only accelerator focused on the global semiconductor industry, Tarun outlined the sector’s resurgence, persistent… Read More
This is a clear reminder of how important the semiconductor ecosystem is and how closely TSMC works with customers. The TSMC Symposium started 30 years ago and I have been a part of it ever since. This event is attended by TSMC’s top customers and partners and is the #1 semiconductor networking event of the year, absolutely.… Read More
Modern chip design has reached unprecedented levels of complexity. Today’s System-on-Chip (SoC) designs integrate multiple processors, complex memory hierarchies, sophisticated interconnects, and much more. All requiring orchestration using complex EDA tool flows. Months are routinely lost to configuration… Read More
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Quantum Computing Technologies and Challenges