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Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
by Daniel Nenni on 01-20-2026 at 6:00 am

Pushing the Packed SIMD Extension Over the Line Andes RISCV Summit

The rapid growth of signal processing workloads in embedded, mobile, and edge computing systems has intensified the need for efficient, low-latency computation. Rich Fuhler’s update on the RISC-V Packed SIMD extension highlights why scalar SIMD digital signal processing (DSP) instructions are becoming a critical architectural… Read More


Verification Futures with Bronco AI Agents for DV Debug

Verification Futures with Bronco AI Agents for DV Debug
by Daniel Nenni on 01-16-2026 at 6:00 am

Bronco AI Verification Futures 2025

Verification has become the dominant bottleneck in modern chip design. As much as 70% of the overall design cycle is now spent on verification, a figure driven upward by increasing design complexity, compressed schedules, and a chronic shortage of design verification (DV) engineering bandwidth. Modern chips generate thousands… Read More


Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering

Last Call: Why Your Real‑World Lessons Belong in DAC 2026’s Engineering
by Admin on 01-15-2026 at 6:00 am

DAC Call for Contributions 2026

By Frank Schirrmeister, Synopsys
Disclaimer: This article is written in my role as Engineering Track Chair for DAC 2026

If you’ve ever walked out of DAC with a handful of practical ideas you could put to work when you return to work, you already know the value of the Engineering Track. It’s where practitioners talk to practitioners… Read More


CES 2026 and all things Cycling

CES 2026 and all things Cycling
by Daniel Payne on 01-11-2026 at 2:00 pm

segway

I just completed the annual Rapha 500 Challenge on Strava by cycling 869 km in eight days, so it’s time to give you my annual recap of CES 2026 and all things cycling. Similar to previous years the big push again in 2026 are e-bikes and even e-motos. The AI acronym was everywhere too in product names and announcements as physical… Read More


Podcast EP326: How PhotonDelta is Advancing the Use of Photonic Chip Technology with Jorn Smeets

Podcast EP326: How PhotonDelta is Advancing the Use of Photonic Chip Technology with Jorn Smeets
by Daniel Nenni on 01-09-2026 at 10:00 am

Daniel is joined by Jorn Smeets, Managing Director for North America at PhotonDelta, an industry accelerator for photonic chip technology. Based in Silicon Valley, his mission is to advance the photonic chip industry by fostering collaboration between European and North American entities.

Dan explores the focus of PhotonDelta… Read More


Webinar: Why AI-Assisted Security Verification For Chip Design is So Important

Webinar: Why AI-Assisted Security Verification For Chip Design is So Important
by Mike Gianfagna on 01-09-2026 at 6:00 am

Why AI Assisted Security Verification For Chip Design is So Important

It is well-known that AI is everywhere, and the incredible power of this new technology is enabled by highly complex, purpose-built silicon. But there is a silent enemy of this substantial, world-changing progress. Something that has the power to steal a bright future from all of us. The hardware root of trust for those advanced… Read More


Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML

Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and ML
by Daniel Nenni on 01-08-2026 at 6:00 am

Nvidia Overcoming the Challenges of Blending Hardware Verification Expertise with AI and Machine Learning

Hardware verification has always been one of the most demanding phases of system design, but today it faces an unprecedented crisis. As hardware systems grow exponentially in complexity verification resources, time, compute, and human expertise, scale far more slowly. This widening gap has resulted in endless regression … Read More


Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation

Acceleration of Complex RISC-V Processor Verification Using Test Generation Integrated with Hardware Emulation
by Daniel Nenni on 01-06-2026 at 8:00 am

Acceleration of Complex RISC V Processor Verification Using Test Generation Integrated with Hardware Emulation Synopsys

The rapid evolution of RISC-V processors has introduced unprecedented verification challenges. Modern high-end RISC-V cores now incorporate complex features such as vector and hypervisor extensions, virtual memory systems, multi-level caches, advanced interrupt architectures, and multi-hart out-of-order execution.… Read More


Revolutionizing Hardware Design Debugging with Time Travel Technology

Revolutionizing Hardware Design Debugging with Time Travel Technology
by Daniel Nenni on 01-02-2026 at 6:00 am

DVCon Europe 2025 Undo.io

In the semiconductor industry High-Level Synthesis (HLS) and SystemC have become essential tools, allowing engineers to model complex hardware designs using familiar C/C++ constructs. Yet, despite the widespread adoption of these languages, the debugging workflows in hardware development lag far behind those in software… Read More


Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing

Addressing Silent Data Corruption (SDC) with In-System Embedded Deterministic Testing
by Daniel Nenni on 01-01-2026 at 10:00 am

Siemens Broadcom TSMC OIP2025 SemiWiki

Silent Data Corruption (SDC) represents a critical challenge in modern semiconductor design, particularly in high-performance computing environments like AI data centers. As highlighted in a collaborative presentation by Broadcom Inc. and Siemens EDA at the 2025 TSMC OIP event, SDC occurs when hardware defects cause erroneous… Read More