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Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026

Accellera Strengthens Industry Collaboration and Standards Leadership at DVCon U.S. 2026
by Daniel Nenni on 02-10-2026 at 10:00 am

dvconus26 digital ad 800 (3)

At DVCon U.S. 2026, Accellera Systems Initiative reinforces its central role in shaping the future of electronic design and verification through a focused program of workshops, tutorials, and community engagement. As system complexity continues to rise across AI, automotive, HPC, and communications markets, the need for… Read More


Chiplets Reach an Architectural Turning Point at Chiplet Summit 2026

Chiplets Reach an Architectural Turning Point at Chiplet Summit 2026
by Daniel Nenni on 02-09-2026 at 10:00 am

Chiplet Summit 2026

The semiconductor industry’s transition toward chiplet-based architectures is entering a decisive new phase. What began as a promising alternative to SoC design is now confronting real-world demands around system integration, validation, and long-term scalability. At Chiplet Summit 2026, taking place February 17–19 … Read More


Gate-All-Around (GAA) Technology for Sustainable AI

Gate-All-Around (GAA) Technology for Sustainable AI
by Daniel Nenni on 02-09-2026 at 8:00 am

Gate All Around Technology for Sustainable AI SemiWiki

The transition from FinFET to Gate-All-Around (GAA) transistor technology represents a pivotal moment in the evolution of logic devices, driven by both physical scaling limits and the rapidly growing computational demands of artificial intelligence. As semiconductor technology approaches the sub-3 nm regime, traditional… Read More


Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen

Podcast EP330: An Overview of DVCon U.S. 2026 with Xiaolin Chen
by Daniel Nenni on 02-06-2026 at 10:00 am

Daniel is joined by Xiaolin Chen, Senior Director of Technical Product Management for Formal Solutions at Synopsys. She has over 20 years of experience applying formal technology in verification and partnering with customers to identify opportunities where formal methods are best suited to solve complex verification challenges.… Read More


The Launch of RISC-V Now! A New Chapter in Open Computing

The Launch of RISC-V Now! A New Chapter in Open Computing
by Daniel Nenni on 02-04-2026 at 8:00 am

RISC Now Andes

On February 3, 2026, Andes Technology officially announced the launch of RISC-V Now!, a new global conference series designed around the next phase of RISC-V adoption: real-world deployment and commercial scaling. This initiative marks a shift from exploratory and research-focused events toward practical, production-oriented… Read More


The 71st International Electron Devices Meeting (IEDM 2025)

The 71st International Electron Devices Meeting (IEDM 2025)
by Daniel Nenni on 02-03-2026 at 6:00 am

IEDM 2025 SemiWiki

It is hard to believe this conference is older than most all of the participants, including myself. The amount of history behind this conference is amazing. Back in 1955 the meeting began as the Electron Devices Meeting (EDM), organized by what later became the IEEE Electron Devices Society. Its core purpose was to bring together… Read More


TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor Innovation

TSMC’s 2026 AZ Exclusive Experience Day: Bridging Careers and Semiconductor Innovation
by Daniel Nenni on 02-02-2026 at 8:00 am

TSMC AZ Day FAB 21

In February of 2026, Taiwan Semiconductor Manufacturing Company (TSMC) will host the TSMC AZ Exclusive Experience Day in Phoenix, Arizona, offering selected participants a rare opportunity to engage directly with one of the most advanced semiconductor manufacturing organizations in the world. The event will serve as an immersive… Read More


DAC – The Chips to Systems Conference 2026

DAC – The Chips to Systems Conference 2026
by Daniel Nenni on 02-02-2026 at 6:00 am

DAC 2026 Long Beach

The Design Automation Chips to Systems Conference is the preeminent international event for professionals involved in electronic design, system architecture, and EDA.  Formerly known simply as the Design Automation Conference or DAC has evolved over more than six decades into a forward-looking forum that spans the entire… Read More


Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension
by Daniel Nenni on 01-20-2026 at 6:00 am

Pushing the Packed SIMD Extension Over the Line Andes RISCV Summit

The rapid growth of signal processing workloads in embedded, mobile, and edge computing systems has intensified the need for efficient, low-latency computation. Rich Fuhler’s update on the RISC-V Packed SIMD extension highlights why scalar SIMD digital signal processing (DSP) instructions are becoming a critical architectural… Read More


Verification Futures with Bronco AI Agents for DV Debug

Verification Futures with Bronco AI Agents for DV Debug
by Daniel Nenni on 01-16-2026 at 6:00 am

Bronco AI Verification Futures 2025

Verification has become the dominant bottleneck in modern chip design. As much as 70% of the overall design cycle is now spent on verification, a figure driven upward by increasing design complexity, compressed schedules, and a chronic shortage of design verification (DV) engineering bandwidth. Modern chips generate thousands… Read More