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Crescent Island: Turning Memory Capacity into Agentic AI Throughput

Crescent Island: Turning Memory Capacity into Agentic AI Throughput
by Admin on 08-27-2026 at 2:00 pm

Intel Crecesent Island Hot Chips 2026

Intel’s Crescent Island is a discrete data-center GPU designed for agentic AI inference, where performance is constrained by more than matrix arithmetic. Multi-step agents impose latency through repeated model calls and tool interactions, consume large memory capacity for weights and long-context key-value caches, and… Read More


Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon

Intel Diamond Rapids: Building Xeon Up, Out, and Through Silicon
by Admin on 08-26-2026 at 2:00 pm

Intel Diamond Rapids Hot Chips 2026

Akhilesh Kumar & Krishnakanth Sistla, Intel

Diamond Rapids is Intel’s next-generation Xeon processor, designed around the proposition that hyperscale performance increasingly depends on moving, processing, and protecting data as efficiently as executing instructions. The architecture replaces the conventional… Read More


Bronco AI at DAC 2026, What a Difference a Year Makes

Bronco AI at DAC 2026, What a Difference a Year Makes
by Mike Gianfagna on 08-26-2026 at 6:00 am

Bronco AI at DAC 2026, What a Difference a Year Makes

During my time at DAC 2026 I felt like I was attending two events. One was the traditional DAC where approaches to designing complex chips using the best tools and methodologies were the focus. There was another focus for the conference. This one was like the traditional DAC with an important difference. Here, the discussion centered… Read More


Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance

Intel Wildcat Lake: Right-Sizing Silicon Without Sinking Performance
by Admin on 08-25-2026 at 2:00 pm

Intel Wildcat Hot Chips 2026

Lance Hacking, Intel

Intel Core Series 3, code-named Wildcat Lake, is a mainstream client system-on-chip derived from the Panther Lake-based Core Ultra Series 3 architecture. Its design objective is not maximum feature density, but broad deployment of current-generation CPU, graphics, AI, memory, security, and connectivity… Read More


Webinar: Warpage has a Timing Problem

Webinar: Warpage has a Timing Problem
by Daniel Nenni on 08-25-2026 at 9:00 am

Thermo mechanical (1)

In advanced packaging, warpage is rarely a modeling problem. It is a timing problem.

JOHN BRUGGEMAN


By the time many advanced packages undergo high-fidelity thermo-mechanical analysis, a long chain of decisions has already been made. Stackup. Materials. Die placement. Package architecture. Each decision constrains the Read More


RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026

RISC-V at Sixteen: From Modular ISA to Standardized Platforms at Hot Chips 2026
by Admin on 08-24-2026 at 12:00 pm

RISC V at 16 Hot Chips

RISC-V has evolved from a Berkeley research architecture into a global instruction-set standard spanning embedded controllers, application processors, accelerators, and emerging servers. Its defining technical characteristic is not merely openness, but disciplined modularity. Four ratified base ISAs—RV32I, RV64I,… Read More


Hot Chips: Evolving Memory Architectures for Artificial Intelligence

Hot Chips: Evolving Memory Architectures for Artificial Intelligence
by Admin on 08-24-2026 at 10:00 am

Evolving Memory Architectures for AI Hot CHips 2026

Artificial intelligence performance is increasingly constrained by memory rather than arithmetic throughput. Scaling laws show that model quality improves when parameter count, training data, and compute grow together, but this balance fails when processors cannot obtain operands quickly enough. Contemporary accelerators… Read More


What Hot Chips 2026 Tells Us About What Silicon Valley Is Actually Building

What Hot Chips 2026 Tells Us About What Silicon Valley Is Actually Building
by Jonah McLeod on 08-23-2026 at 6:00 pm

What Hot Chips Tells us 2026

Here’s what the presentations selected for the 2026 Hot Chips Conference tell us about what Silicon Valley companies are doing these days.

The conference, running this week at Stanford’s Memorial Auditorium, doesn’t publish detailed abstracts ahead of time, but the program itself, just the lineup of who’s presenting what, … Read More


Agentrys Shows You How to Build a Multi-Agent System in 30 Minutes

Agentrys Shows You How to Build a Multi-Agent System in 30 Minutes
by Mike Gianfagna on 08-20-2026 at 2:00 pm

Agentrys Shows You How to Build a Multi Agent System in 30 Minutes

Agentrys believes that a purpose-built multi-agent system for chip design shouldn’t be a quarter-long project. Agentic AI systems are becoming quite popular to cut design time and increase quality for complex chip design projects. The challenge is finding the right agentic flow for a particular application. There are… Read More


Reducing EUV Exposure Dose Through Underlayer Engineering

Reducing EUV Exposure Dose Through Underlayer Engineering
by Admin on 08-20-2026 at 2:00 pm

Reducing EUV Exposure Dose Through Underlayer Engineering

Extreme-ultraviolet lithography is essential for manufacturing advanced semiconductor devices, but its continued scaling presents a difficult materials problem. Photoresists must simultaneously provide high resolution, low exposure dose, limited line-edge or linewidth roughness, and extremely low defectivity. … Read More