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Q2FY24TessentAI 800X100
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Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks

Securing PCIe Transaction Layer Packet (TLP) Transfers Against Digital Attacks
by Kalar Rajendiran on 06-01-2023 at 10:00 am

PCIe TLP Encryption

In the fast moving world of data communications, the appetite for high speed data transfers is accompanied by a growing need for data confidentiality and integrity. The wildly popular PCIe interface standard for connectivity has not only been increasing data transfer rates but has also introduced an Integrity and Data Encryption… Read More


Emerging Stronger from the Downturn

Emerging Stronger from the Downturn
by Kalar Rajendiran on 05-16-2023 at 6:00 am

Full Flow from HL Synthesis through to GDSII Accelerates the creation of AI IP

It was refreshing to hear a talk focused on emerging stronger from the downturn when the news and media are focused on the gloom. At the recent Siemens EDA User2User conference, Joe Sawicki, executive vice president, IC, gave an uplifting keynote talk to the audience. He highlighted a secular growth trend happening in the semiconductor… Read More


Chiplet Modeling and Workflow Standardization Through CDX

Chiplet Modeling and Workflow Standardization Through CDX
by Kalar Rajendiran on 05-15-2023 at 6:00 am

Chiplet Integration Workflow

Chiplet is a hot topic in the semiconductor world these days. So much so that if one hasn’t heard that term, the person must be living on a very isolated islet. Humor aside, products built using chiplets-based methodology have been in existence for at least some years now. Companies such as Intel, AMD, Apple and others have integrated… Read More


Tessent SSN Enables Significant Test Time Savings for SoC ATPG

Tessent SSN Enables Significant Test Time Savings for SoC ATPG
by Kalar Rajendiran on 05-08-2023 at 6:00 am

Pattern Generation Block Level ATPG Flow

SoC test challenges arise due to the complexity and diversity of the functional blocks integrated into the chip. As SoCs become more complex, it becomes increasingly difficult to access all of the functional blocks within the chip for testing. SoCs also can contain billions of transistors, making it extremely time-consuming… Read More


Using ML for Statistical Circuit Verification

Using ML for Statistical Circuit Verification
by Daniel Payne on 05-03-2023 at 10:00 am

6 sigma samples statistical circuit

I’ve been following Solido as a start-up EDA vendor since 2005, then they were acquired by Siemens in 2017. At the recent User2User event there was a presentation by Kwonchil Kang, of Samsung Electronics on the topic, ML-enabled Statistical Circuit Verification Methodology using Solido. For high reliability circuits… Read More


Achieving Optimal PPA at Placement and Carrying it Through to Signoff

Achieving Optimal PPA at Placement and Carrying it Through to Signoff
by Kalar Rajendiran on 05-02-2023 at 10:00 am

PreRoute PostRoute Net Length Correlation

Performance, Power and Area (PPA) metrics are the driving force in the semiconductor market and impact all electronic products that are developed. PPA tradeoff decisions are not engineering decisions, but rather business decisions made by product companies as they decide to enter target end markets. As such, the sooner a company… Read More


Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links

Mitigating the Effects of DFE Error Propagation on High-Speed SerDes Links
by Kalar Rajendiran on 04-18-2023 at 10:00 am

Pre and Post FEC BER as FEC Matrix size Reduces

As digital transmission speeds increase, designers use various techniques to improve the signal-to-noise ratio at the receiver output. One such technique is the Decision Feedback Equalizer (DFE) scheme, commonly used in high-speed Serializer-Deserializer (SerDes) circuits to mitigate the effects of channel noise and … Read More


Hardware Root of Trust for Automotive Safety

Hardware Root of Trust for Automotive Safety
by Daniel Payne on 04-13-2023 at 10:00 am

Rambus, RT 640,

Traveling by car is something that I take for granted and I just expect that my trips will be safe, yet our cars are increasingly using dozens of ECUs, SoCs and millions of lines of software code that combined together present a target for hackers or system failures. The Automotive Safety Integrity Levels (ASIL) are known by the letters:… Read More


Siemens EDA on Managing Verification Complexity

Siemens EDA on Managing Verification Complexity
by Bernard Murphy on 04-13-2023 at 6:00 am

2023 DVCon Harry Foster

Harry Foster is Chief Scientist in Verification at Siemens EDA and has held roles in the DAC Executive Committee over multiple years. He gave a lunchtime talk at DVCon on the verification complexity topic. He is an accomplished speaker and always has a lot of interesting data to share, especially his takeaways from the Wilson Research… Read More


Siemens Keynote Stresses Global Priorities

Siemens Keynote Stresses Global Priorities
by Bernard Murphy on 03-27-2023 at 6:00 am

Space Perspective

Dirk Didascalou, Siemens CTO, gave a keynote at DVCon, raising our perspective on why we do what we do. Yes, our work in semiconductor design enables the cloud and 5G and smart everything, but these technologies push progress for a select few. What about the big global concerns that affect us all: carbon, climate, COVID and conflict?… Read More