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The silent killer of analog reliability: Why SPICE misses floating net

The silent killer of analog reliability: Why SPICE misses floating net
by Admin on 10-08-2026 at 6:00 am

87450 fig1 top level odo schematic

By Bhanu Pandey

The semiconductor industry is currently facing a significant challenge in functional verification. According to the most recent Wilson Research Group / Siemens EDA Functional Verification Study, first-silicon success rates have hit a historic low, with nearly 68% of designs requiring two or more spins. While… Read More


Wilson Survey Signals Need for New Understanding of Verification Success

Wilson Survey Signals Need for New Understanding of Verification Success
by Bernard Murphy on 10-07-2026 at 6:00 am

Siemens Wilson first silicon success

Siemens has again sponsored a Wilson-led survey on the state of (functional) verification in the industry, and this time Harry Foster (Chief Scientist, Verification at Siemens) has condensed his major takeaways from the report. These are intriguing – particularly an apparent revolutionary change in first-silicon trends.… Read More


Beyond the Die: Verifying the Connected Chip

Beyond the Die: Verifying the Connected Chip
by Daniel Nenni on 10-06-2026 at 10:00 am

Efficient, Scalable Methodology for Reliability and ESD Verification of Complex 3D IC CoWoS Systems

One of the standout presentations at the 2026 TSMC OIP Forum highlighted a collaboration between Siemens EDA, Marvell, and TSMC. I always appreciate EDA presentations that bring together customer and foundry perspectives, and this one did not disappoint. We follow 3D IC technology closely and have published more than 150 blogs… Read More


Siemens CTO update on Calibre at DAC 2026

Siemens CTO update on Calibre at DAC 2026
by Daniel Payne on 10-05-2026 at 10:00 am

Juan Rey

At DAC 2026 I had the opportunity to speak with Juan Rey, CTO Siemens EDA about the Calibre product used for IC physical verification, circuit verification, 3D IC and DFM optimization. Juan has been involved with Calibre since 2001, served on the Board of Directors of Silicon Integration Initiative (SI2), on the Executive Technology… Read More


Siemens and TSMC push AI deeper into chip design

Siemens and TSMC push AI deeper into chip design
by Daniel Nenni on 09-29-2026 at 8:00 am

Siemens and TSMC push AI deeper into chip design

Siemens and TSMC are expanding their collaboration on semiconductor design tools, with a focus on AI assisted workflows, advanced chip packaging and support for newer manufacturing processes. Their announcement centers on an AI agent intended to find and fix design rule violations: errors that can prevent a chip layout from… Read More


From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters

From Custom Silicon to AI Systems: Why Cross-Layer Engineering Matters
by Daniel Nenni on 09-24-2026 at 8:00 am

From Custom Silicon to AI Systems Why Cross Layer Engineering Matters

The central argument of Ankur Gupta’s AI Infra Summit keynote is simple but consequential: the next leap in AI infrastructure will not come from improving chips, servers, cooling systems, or data centers independently. It will come from optimizing the connections among them. Siemens frames this as a journey “from custom silicon… Read More


The Invisible Bottleneck Is Costing You Time You Can’t Get Back

The Invisible Bottleneck Is Costing You Time You Can’t Get Back
by Joel Jorgensen on 09-17-2026 at 8:00 am

invisible bottle neck package

The 2026 Siemens EDA and Wilson Research Group study just came out. Verification now eats close to half the schedule on every IC and FPGA program. I don’t doubt that number. What I don’t know is how much of it is actually verification, and how much of it is something else showing up disguised as verification.

Sometimes… Read More


DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better

DAC 2026: A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better
by Mike Gianfagna on 09-02-2026 at 6:00 am

DAC 2026 A Discussion of Who Owns the Intelligence Behind Tomorrow’s Chips and How to Make it Better

The industry is moving from simple documentation chatbots to agentic workflows capable of performing complex, multi-step tasks like design creation, verification, and library characterization. These agents are intended to enhance engineering productivity by roughly 50%. A panel of industry experts met at DAC to discuss… Read More


Questa One Updated at DAC 2026

Questa One Updated at DAC 2026
by Daniel Payne on 08-20-2026 at 10:00 am

questa one dac2026

Abhi Kolpekwar, VP & General Manager, Digital Verification Technologies at Siemens EDA met with me at #DAC2026 to provide the big picture on smart verification tools, something they call Questa One. Their verification tools are infused with AI to improve productivity on projects like SoCs, 3D IC and chiplets. Abhi shared… Read More


Siemens and NVIDIA tout Agentic AI

Siemens and NVIDIA tout Agentic AI
by Daniel Payne on 08-11-2026 at 10:00 am

siemens nvidia dac2026

Siemens has EDA tools and flows, NVIDIA has AI infrastructure, so what happens when these two companies collaborate? I’m at DAC 2026 and all the buzz this year is Agentic AI, so an came out on Sunday evening about how semiconductor and PCB design flows are being improved by this teamwork. Amit Gupta from Siemens and Timothy Costa from… Read More