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Q2FY24TessentAI 800X100
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Visualizing hidden parasitic effects in advanced IC design 

Visualizing hidden parasitic effects in advanced IC design 
by Admin on 10-15-2025 at 10:00 am

[white paper] Parasitic Analysis Figures

By Omar Elabd

As semiconductor designs move below 7 nm, parasitic effects—resistance, capacitance and inductance—become major threats to IC performance and reliability, often hiding where netlist reviews cannot reach. Design teams need advanced visualization tools like heat maps, layer-based analysis and direct layout… Read More


Protect against ESD by ensuring latch-up guard rings

Protect against ESD by ensuring latch-up guard rings
by Admin on 10-13-2025 at 10:00 am

fig1 latchup event

By Mark Tawfik

Overview: Protecting ICs from costly ESD and latch-up failures

Electrostatic discharge (ESD) events cost the semiconductor industry an estimated $8 billion annually in lost productivity, warranty claims and product failures [1].

Ensuring the robust protection of integrated circuits (ICs) against various… Read More


Something New in Analog Test Automation

Something New in Analog Test Automation
by Daniel Payne on 09-16-2025 at 10:00 am

IJTAG min

Digital design engineers have used DFT automation technologies like scan and ATPG for decades now, however, analog blocks embedded within SoCs have historically required that a test engineer write tests that require specialized expertise and that can take man-months to debug. Siemens has a long history in the DFT field, SPICE… Read More


Tessent MemoryBIST Expands to Include NVRAM

Tessent MemoryBIST Expands to Include NVRAM
by Mike Gianfagna on 09-10-2025 at 10:00 am

Tessent MemoryBIST Expands to Include NVRAM

The concept of built-in self-test for electronics has been around for a while. An article in Electronic Design from 1996 declared that, “built-in self-test (BIST) is nothing new.” The memory subsystem is a particularly large and complex part of any semiconductor design, and it’s one that can be particularly vexing to test. Design… Read More


Smart Verification for Complex UCIe Multi-Die Architectures

Smart Verification for Complex UCIe Multi-Die Architectures
by Admin on 09-08-2025 at 10:00 am

Figure 1

By Ujjwal Negi – Siemens EDA

Multi-die architectures are redefining the limits of chip performance and scalability through the integration of multiple dies into a single package to deliver unprecedented computing power, flexibility, and efficiency. At the heart of this transformation is the Universal Chiplet Interconnect… Read More


Orchestrating IC verification: Harmonize complexity for faster time-to-market

Orchestrating IC verification: Harmonize complexity for faster time-to-market
by Admin on 09-01-2025 at 6:00 am

fig1 optimize ic with mjs

By Marko Suominen and Slava Zhuchenya of Siemens Digital Industries Software.

It’s often said that an orchestra without a conductor is just a collection of talented individuals making noise. The conductor’s role is to transform that potential cacophony into a unified, beautiful symphony. The same concept holds… Read More


Perforce and Siemens at #62DAC

Perforce and Siemens at #62DAC
by Daniel Payne on 08-28-2025 at 10:00 am

perforce siemens min

Wednesday was the last day at #62DAC for me and I attended an Exhibitor Session entitled, Engineering the Semiconductor Digital Thread, which featured Vishal Moondhra, VP Solutions Engineering of Perforce IPLM and Michael Munsey, VP Semiconductor Industry at Siemens Digital Industries. Instead of just talking from slides,… Read More


Breaking out of the ivory tower: 3D IC thermal analysis for all

Breaking out of the ivory tower: 3D IC thermal analysis for all
by Admin on 08-26-2025 at 6:00 am

figure 1

Todd Burkholder and Andras Vass-Varnai, Siemens EDA

As semiconductor devices become smaller, more powerful and more densely integrated, thermal management has shifted from an afterthought to a central challenge in modern IC design. In contemporary 3D IC architectures—where multiple chiplets are stacked and closely arrayed—power… Read More


Software-defined Systems at #62DAC

Software-defined Systems at #62DAC
by Daniel Payne on 08-06-2025 at 10:00 am

siemens panel on software-defined systems min

Modern EVs are prime examples of software-defined systems, so I attended a #62DAC panel session hosted by Siemens to learn more from experts at Collins Aerospace, Arm, AMD and Siemens. Here’s the list of panelists that span several domains, and what follows is my paraphrase of the discussion topics.

Panel Discussion

Q: How does… Read More


DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA

DAC TechTalk – A Siemens and NVIDIA Perspective on Unlocking the Power of AI in EDA
by Mike Gianfagna on 08-05-2025 at 6:00 am

Screenshot

AI was everywhere at DAC. Presentations, panel discussions, research papers and poster sessions all had a strong dose of AI. At the DAC Pavillion on Monday two heavy weights in the industry, Siemens and NVIDIA took the stage to discuss AI for design, both present and future.  What made this event stand out for me was the substantial… Read More