The upcoming Keysight EDA 2025 launch has three familiar tracks: RF circuit design, high-speed digital circuit design, and device modeling and characterization. However, this update features a common thread between the tracks – AI-enhanced design workflows. AI speeds modeling and simulation, opening co-optimization for… Read More
Electronic Design Automation
CEO Interview: Bijan Kiani of Mach42
Bijan’s role includes overseeing all product groups, field engineering, customer support, strategy, sales, marketing, and business development. His previous appointments include VP of Marketing at Synopsys Design Group and CEO of InCA. He holds a PhD in Electrical Engineering.
Tell us about your company
Mach42 is a verification… Read More
Changing RISC-V Verification Requirements, Standardization, Infrastructure
A lively panel discussion about RISC-V and open-source functional verification highlighted this year’s Design Automation Conference. Part One looked at selecting a RISC-V IP block from a third-party vendor and investigating its functional verification process.
In Part Two, moderator Ron Wilson and Contributing Editor … Read More
Synopsys-Ansys 2.5D/3D Multi-Die Design Update: Learning from the Early Adopters
The demand for high-performance computing (HPC), data centers, and AI-driven applications has fueled the rise of 2.5D and 3D multi-die designs, offering superior performance, power efficiency, and packaging density. However, these benefits come with myriads of challenges, such as multi-physics, which need to be addressed.… Read More
Podcast EP259: A View of the History and Future of Semiconductor Manufacturing From PDF Solution’s John Kibarian
Dan is joined by John Kibarian, president, chief executive officer and co-founder of PDF Solutions. He has served as president since 1991 and CEO since 2000.
John explains the evolution of PDF Solutions from its beginnings in 1992 to the present day. John describes moving from TCAD tools for design teams to a yield optimization … Read More
New Product for In-System Test
The annual ITC event is happening this week in San Diego as semiconductor test professionals gather from around the world to discuss their emerging challenges and new approaches, so last week I had the opportunity to get an advance look at something new from Siemens named Tessent In-System Test software. Jeff Mayer, Product Manager,… Read More
An Illuminating Real Number Modeling Example in Functional Verification
I just read an interesting white paper on functional verification of analog blocks using SV-RNM (SystemVerilog real number modeling). The content is worth the effort to read closely as it elaborates a functional verification flow for RNM matching expectations for digital logic verification, from randomization to functional… Read More
Adding an AI Assistant to a Hardware Language IDE
I’ve been working with AMIQ EDA for several years, and have frequently been impressed by new capabilities in their Design and Verification Tools Integrated Development Environment (DVT IDE) family. They just announced AI Assistant, which leverages large language model (LLM) technology. LLMs are much in the news these days,… Read More
The Next LLM Architecture? Innovation in Verification
LLMs have amazing capabilities but inference run times grow rapidly with the size of the input (prompt) sequence, a significant weakness for some applications in engineering. State space models (SSMs) aim to correct this weakness. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur,… Read More
How to Update Your FPGA Devices with Questa
It’s a fact of life that technology marches on. Older process nodes get replaced by newer ones. As a result, ASSPs and FPGAs are obsoleted, leaving behind large system design investments that need to re-done. Since many of these obsolete designs are performing well in the target application, this re-do task can be particularly … Read More


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