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LUBIS EDA SemiWiki Banner
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Assertion IP (AIP) for Improved Design Verification

Assertion IP (AIP) for Improved Design Verification
by Daniel Payne on 10-14-2025 at 10:00 am

Detailed flow min

Over the years design reuse methodology created a market for Semiconductor IP (SIP), now with formal techniques there’s a need for Assertion IP (AIP). Where each AIP is a reusable and configurable verification component used in hardware design to detect protocol and functional violations in a Design Under Test (DUT).  LUBIS … Read More


LUBIS EDA at the 2025 Design Automation Conference #62DAC

LUBIS EDA at the 2025 Design Automation Conference #62DAC
by Daniel Nenni on 06-12-2025 at 6:00 am

62nd DAC SemiWiki

At the Design Automation Conference (DAC) 2025 in San Francisco, LUBIS EDA returns as an exhibitor to showcase its latest innovations in formal verification automation, helping semiconductor teams move faster and with more confidence through the most complex verification challenges.

LUBIS EDA is a fast-growing EDA startup… Read More


Automating Formal Verification

Automating Formal Verification
by Daniel Payne on 01-30-2025 at 10:00 am

LUBIS on cloud min

Formal verification methods are being adopted at a fast pace as a complement to traditional verification methods like functional simulation for IP blocks in SoC designs. I had a video meeting with Max Birtel, co-founder of LUBIS EDA and learned more about their history, products and vision. This company started recently in 2020… Read More


CEO Interview: Tobias Ludwig of LUBIS EDA

CEO Interview: Tobias Ludwig of LUBIS EDA
by Daniel Nenni on 10-11-2024 at 6:00 am

IMG 3442 eh

Tobias began his journey with a strong academic foundation in electronic design automation, studying at a leading university in Germany that specialized in formal verification. After graduating, Tobias gained hands-on experience in the semiconductor industry, where he quickly recognized the challenges and inefficiencies… Read More