Recently, a partnership between Achronix and Bluespec has been in the news. Bluespec RISC-V processors are available as soft cores in a Speedster®7t FPGA on Achronix’s VectorPath® PCIe development card or in a standalone Speedster7t FPGA. We spoke with executives from Achronix and Bluespec about the impetus for this effort … Read More
Author: Don Dingee
INTERVIEW: Bluespec RISC-V soft cores in Achronix FPGAs
ARC-V portfolio plus mature software IP targets three tiers
Synopsys is bridging its long-running ARC® processor IP strategy into a RISC-V architecture – Bernard Murphy introduced the news here on SemiWiki last November. We’re getting new insight from Synopsys on its ARC-V™ portfolio and how they see RISC-V IP plus their mature software development toolchain IP fitting customer needs… Read More
The latest ideas on time-sensitive networking for aerospace
Time-sensitive networking for aerospace and defense applications is receiving new attention as a new crop of standards and profiles approaches formal release, anticipated before the end of 2024. CAST, partnering with Fraunhofer IPMS, has developed a suite of configurable IP for time-sensitive networking (TSN) applications,… Read More
Self-heating and trapping enhancements in GaN HEMT models
High-fidelity models incorporating real-world, cross-domain effects are essential for accurate RF system simulation. The surging popularity of gallium nitride (GaN) technology in 5G base stations, satellite communication, defense systems, and other applications raises the bar for transistor modeling. Keysight dives… Read More
WEBINAR: The Rise of the DPU
The server and enterprise network boundary has seen complexity explode in recent years. What used to be a simple TCP/IP offload task for network interface cards (NICs) is transforming into full-blown network acceleration using a data processing unit (DPU), able to make decisions based on traffic routes, message content, and… Read More
Ultra-low-power MIPI use case for streaming sensors
MIPI built its reputation on the efficient streaming of data from camera sensors in mobile devices. It combines high-speed transfers with balanced power consumption, helping extend battery life while providing the responsiveness users expect. However, high speed is not the only mode of operation for a MIPI interface – specifications… Read More
QuantumPro unifies superconducting qubit design workflow
To create quantum computing chips today, a typical designer must cobble various tools together, switching back and forth between them for different tasks. By contrast, EDA solutions such as Keysight Advanced Design System (ADS) unify a design workflow in a single interface with automated data exchange between features. In … Read More
Chiplet ecosystems enable multi-vendor designs
Chiplets dominate semiconductor industry conversations right now – and after the recent Chiplet Summit, we expect the intensity to go up a couple of notches. One company name often heard is Blue Cheetah, and we had the opportunity to sit down with them recently to discuss their views and their just-announced design win at Tenstorrent.… Read More
WEBINAR: FPGA-Accelerated AI Speech Recognition
The three-step conversational AI (CAI) process – automatic speech recognition (ASR), natural language processing, and text-to-synthesized speech response – is now deeply embedded in the user experience for smartphones, smart speakers, and other devices. More powerful large language models (LLMs) can answer more queries… Read More
NoCs give architects flexibility in system-in RISC-V design
RISC-V tends to generate excitement over the possibilities for the processor core, any custom instruction extensions, and its attached memory subsystem. Those are all necessary steps to obtaining system-level performance. But is that attention sufficient? Architects who have ventured into larger system-on-chip (SoC) … Read More
If you believe in Hobbits you can believe in Rapidus