Senior Design Verification Engineer

Description

Senior Design Verification Engineer with Arteris, Inc. d/b/a Arteris IP (Austin, TX)

Research, design, develop, and test computer-related equipment. Analyze computer test results, modify designs as needed, and update existing computer equipment to align with new software. Define, document and execute system level RTL and coverage verification tests. Develop and debug advanced UVM based testbeds. Contribute to improving and refining the verification process, methodology and metrics. Conduct performance verification and power consumption verification. Perform regression triage, and debug RTL designed in Verilog and System Verilog.  Drive complex SoC projects and testbed development of verification closeout.

Partial remote work permitted with direct reporting to 9601 Amberglen Blvd. Suite 117 Austin, TX 78729.

Requirements: Requires Master’s or Bachelor’s degree in Electrical Engineering, Computer Engineering or related field. Position requires experience (3 years with Master’s or 5 with Bachelor’s), which must include some experience in each of the following skills: VHDL, Verilog, System Verilog; Programming languages: C, Java and Python; PERL, MATLAB, HTML; UVM (sequences, tests, drivers, monitors, and scoreboards); ABV assertion-based verification (AMBA-APB, SPI, I2C); and Simvision, Verdi, Perfoce (code repository).