Verification Systems Engineer

Role:

The Verification Systems Engineer plays a pivotal role in functionally verifying bleeding-edge features of the EPU as they are developed, from end to end. You will collaborate closely with micro-architects to gain an intimate, low-level understanding of new hardware features as they are developed. You will leverage this knowledge to develop and maintain software systems to functionally model and verify these features, including targeted directed tests and complex random test benches, written primarily using modern C++ and SystemC. Your experience using the systems you build to detect and diagnose bugs will be critical toward our effort to build fully functional products. You will also document and communicate feature specs to the software team to enable usage of the features you verify, giving you a view of the full stack. Ideal candidates will have a strong background in software development and systems-level programming, as well as knowledge of microarchitectural concepts and a willingness to take initiative to grow and learn more about architecture design and tools.

Responsibilities:

• Define DV requirements for design changes resulting from rapidly evolving AI/ML models; work with engineers across domains to understand real-world use cases
• Partner with other members of the verification, as well as architects and designers, to functionally verify entire blocks of the Quadric EPU by designing, implementing, and maintaining custom directed and random testing systems
• Collaborate directly with micro-architects on new features and develop test plans from scratch
• Develop complex random kernel generators using modern C++
• Maintain CI/CD pipelines to ensure broad test coverage using Python and Jenkins
• Document and communicate the specifications of new hardware features to the software team and support initial efforts to enable usage by programmers