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Physical Design Engineer

Physical Design Engineer
by Admin on 05-19-2023 at 3:38 pm

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Senior Engineer/Principal


  • Generate block level static timing constraints and run STA
  • Build IP floor-plan including pin placement, partitions and power grid.
  • Develop and validate high performance low power clock network guidelines.
  • Perform block level place and route and close the design to meet timing, area and power constraints.
  • Generate and Implement ECOs to fix timing, noise and EM IR violations.
  • Run Physical design verification flow at block level and provide guidelines to fix LVS/DRC violations to other designers.
  • Participate in establishing CAD and physical design methodologies for correct construction designs.

Required Experience

  • Bachelors or Master’s Degree in EE/CS required.
  • 7+ years of Physical Design experience on IP and/or SOC designs.
  • Experience in developing and implementing Power-grid and Clock specifications.
  • Deep knowledge about industry standards and practices in Physical Design, including Physically aware synthesis, floor-planning, and place & route.
  • Deep understanding of scripting languages such as Perl/Tcl,
  • Basic understanding of Extraction and STA methodology and tools.
  • Deep understanding of Physical Design Verification methodology to debug LVS/DRC issues at block level.
  • Strong understanding of all aspects of Physical construction, Integration and Physical Verification.
  • Knowledge of Basic HDL languages like Verilog to be able to work with logic design teams for timing fixes.
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