Principal Hardware Architect

To support our growth, we are looking for a Principal Hardware Architect.

This is a high-level, high-profile position, requiring interaction with cross-functional teams. The work will expose the candidate to all aspects of Network-on-Chip Product design flow, including Architecture, IP development, Network Topology Synthesis, SoC Integration, Performance Modeling, Safety Certifications, Fault Injection, Silicon Testing and other complex SoC product aspects.

Each team is working with the latest tools and digital design and verification techniques in bleeding edge silicon nodes, 5nm and below. Team members work directly with Architecture, Software and SoC teams in Campbell and other global Arteris locations.

As a Principal Hardware Architect at Arteris, you will have opportunity to be part of a team defining and enhancing protocols, synthesis algorithms, and a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. Your role consists into specifying the evolutions of our network-on-chip technology allowing an ever-increasing complexity of SoCs.

You will join a proven-successful company, and be able to influence development environment, architecture, verification, and everything in-between.

 Key Responsibilities

• Write architecture specification for highly configurable network-on-chips with utmost coverage requirements in design verification.
• Develop or upgrade a powerful language and a leading-edge methodology enabling design of extremely configurable IP blocs
• Develop or upgrade interconnect protocols to meet next generation SoC requirements (ie. D2D/C2C, multi-NoC, memory hierarchy…)
• Work closely with modeling and design teams to remain the market leader in NoC performance, power and area.
• Communicate with Hardware, Software and Documentation teams about your changes to ensure product cohesion.
• Maintain and enhance the design development flow methodology and increase automation

We Are Looking For – Key Requirements

• 12+ years of experience in SoC/IP/NoC designs,
• Expert in hardware coherent and non-coherent communication protocols and ordering models (AMBA, PCIe, CXL, OCP, others)
• Expert in ARM and RISC V architectures
• Strong Experience in SoC/IP design flow (e.g. Specification, Architecture, RTL coding, Verification, DFT, Synthesis, Power and Timing Closure),
• Excellent problem solving, strong communication and teamwork skills,
• Self-driven, able to work with minimum supervision.
• Fluent French and English

Education Requirements

PhD or Master’s degree in Science, Engineering or related field.

 Skills

SystemC, GEM5, Verilog / VHDL, System Verilog, Cadence, Synopsys (DC, PTSI, CDC), Mentor Graphic, Matlab, C++, Perl, Tcl, Python.