The semiconductor industry has experienced several defining transitions over the last three decades. We moved from single-core to multicore processors, from ASIC-centric designs to IP-based SoCs, and from monolithic integration to heterogeneous architectures. Today, another transition is underway, one that may ultimately… Read More
Tag: x86
When a Platform Provider Becomes a Competitor: Why Arm’s Silicon Strategy Changes the Incentives
Marc Evans, Director of Business Development & Marketing, Andes Technology USA
I work at a RISC-V IP company, and I genuinely root for Arm — probably more than most people in my position would admit. Not because I’m confused about who competes with whom, but because Arm’s best move for their shareholders is also… Read More
Capability Hardware Enhanced RISC Instructions CHERI Alliance
The CHERI Alliance is a non-profit organization dedicated to accelerating the global adoption of CHERI (Capability Hardware Enhanced RISC Instructions), a technology designed to improve computer security at the hardware level. Established as an independent entity, the Alliance brings together industry leaders, researchers,… Read More
Two Open RISC-V Projects Chart Divergent Paths to High Performance
Up to now the RISC-V community has been developing open-source processor implementations to a stage where they can appeal to system designers looking for alternatives to proprietary Arm and x86 cores. Toward this end, two projects have emerged as particularly significant examples of where RISC-V is heading. One is Ara, a vector… Read More
The Launch of RISC-V Now! A New Chapter in Open Computing
On February 3, 2026, Andes Technology officially announced the launch of RISC-V Now!, a new global conference series designed around the next phase of RISC-V adoption: real-world deployment and commercial scaling. This initiative marks a shift from exploratory and research-focused events toward practical, production-oriented… Read More
RISC-V’s Privileged Spec and Architectural Advances Achieve Security Parity with Proprietary ISAs
Because of its open and modular nature, RISC-V has faced recognizable security challenges stemming from fragmentation, performance inefficiencies, and inherent vulnerabilities. Fragmentation across implementations leads to inconsistencies, making it difficult to enforce uniform security measures. Performance… Read More
Upcoming Webinar: Optimized Chip Design with Main Processors and AI Accelerators
Using the right tool for the job can be extremely important. Well, maybe not in the case of the famed chef Martin Yan who is notorious for using just one knife—a razor sharp wide blade cleaver that doubles as a spatula—for preparing anything and everything he cooks. For the rest of us, though, the right tools can make all the difference.… Read More
Software Developers Turn to CacheQ for Multi-Threading CPU Acceleration
Three-year old CacheQ, founded by two former Xilinx executives and a clever group of engineers, produces a distributed heterogenous compute development environment targeting software developers with limited knowledge of hardware architecture.
The promise of compiler tools for heterogeneous compute systems intrigued… Read More
Apple’s Silicon Switch Changes Game & Balance
Will/should others follow?
TSMC vs Intel impact?
Moving Apple’s supply chain further overseas
Apples move to self served silicon was no surprise…..
It has been speculated for years and we have talked about it many times. It makes more sense for Apple to have silicon, custom designed for their applications and products… Read More
Book Review Mobile Unleashed The History of ARM
After having taken a closer look at x86 processor with “Inside The Machine” I came across “Mobile Unleashed“, a book about the history of a non-Silicon Valley company and technology for a change that has significantly shaped the world of computing as we know it today: ARM.
Written by Daniel Nenni and Don Dingee the book tells the story… Read More
