Transistor-Level Static Checking for Better Performance and Reliability

Transistor-Level Static Checking for Better Performance and Reliability
by Daniel Payne on 05-04-2021 at 10:00 am

power intent checks min

My first transistor-level IC design job was with Intel, doing DRAM designs by shrinking the layout to a smaller process node, and it also required running lots of SPICE runs with manually extracted parasitics to verify that everything was operating OK, meeting the access time specifications and power requirements across PVT … Read More


Stop TDDB from getting through peanut butter

Stop TDDB from getting through peanut butter
by Don Dingee on 01-24-2014 at 6:00 pm

There are a few dozen causes of semiconductor failure. Most can be lumped into one of three categories: material defects, process or workmanship issues, or environmental or operational overstress. Even when all those causes are carefully mitigated, one factor is limiting reliability more as geometries shrink – and it… Read More