Power Analysis from Software to Architecture to Signoff

Power Analysis from Software to Architecture to Signoff
by Daniel Payne on 09-25-2023 at 10:00 am

power analysis min

SoC designs use many levels of design abstraction during their journey from ideation to implementation, and now it’s possible to perform power analysis quite early in the design process. I had a call with William Ruby, Director of Porduct Marketing – Synopsys Low Power Solution to hear what they’ve engineered… Read More


ARM A57 (A53) Virtualizer + IP Accelerated = ?

ARM A57 (A53) Virtualizer + IP Accelerated = ?
by Eric Esteve on 05-12-2015 at 12:00 pm

Hybrid IP Prototyping Kit from Synopsys!
Synopsys has launched IP Accelerated initiative last year. The goal was clearly to accelerate Time-To-Market by providing a complete set of “tools” to augment design productivity:

  • IP Prototyping Kit with reference designs work out-of-the-box
  • IP software development kits enable early
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