Process and device engineers have a tough task to model and simulate an IC process prior to fabricating silicon, however this approach is much better than the alternative choice in the 1970’s of just running multiple lots of wafers and then making measurements to see if your node was meeting specifications. Out of Stanford… Read More
Webinar: Learn How to Use Victory Process TCAD Geometric Etch Models in FinFET and Memory Applications
When: May 18, 2023
Where: Online
Time: 10:00am-10:30am-(PDT)
Language: English
When employing process simulation to generate a complex device structure, TCAD engineers often face the task of reproducing the exact etch profile that has been observed in semiconductor fabrication. Silvaco Victory Process offers several geometric