Foolproof Your IP before it Stumbles in Higher-up Design

Foolproof Your IP before it Stumbles in Higher-up Design
by Pawan Fangaria on 08-06-2015 at 4:00 pm

SoC designs are increasingly becoming assemblies of a large number of IP blocks. A well integrated assembly can lead to a successful PPA (Power, Performance and Area) optimized design. However, it is equally important that each IP block is optimized, robust, and integrable in the design. The complexity of an IP and its integration… Read More