Accelerate Hydrogen Adoption Using Ansys Simulation: Part 3 – Storage / Transport

Accelerate Hydrogen Adoption Using Ansys Simulation: Part 3 – Storage / Transport
by Admin on 03-18-2024 at 2:01 pm

Join us for the third in a four-part series, where we will look at the comprehensive solution for hydrogen storage, from doing a quick assessment of a hydrogen tank filling using a thermal desktop to carrying out detailed 3D simulations of hydrogen leakage and auto-ignition.

The final webinar in the series will cover utilization… Read More


Semiconductor IP QA Standards Get a Boost at #53DAC

Semiconductor IP QA Standards Get a Boost at #53DAC
by Daniel Payne on 06-22-2016 at 12:00 pm

At the #53DAC earlier this month held in Austin, Texas I met up with Renee Donkers, the founder of Fractal Technologies. His company has been focused on improving the quality of semiconductor IP cells through the use of automated checking software. The highest area of growth in EDA as measured by the ESD Alliance is in the reusable… Read More


DRC Concept for IP Qualification and SoC Integration

DRC Concept for IP Qualification and SoC Integration
by Pawan Fangaria on 05-30-2016 at 7:00 am

In the history of semiconductor design and manufacturing, the age-old concept of DRC rule-deck qualification for handshake between design and manufacturing still applies strongly to produce working silicon. In fact, DRC clean GDSII works as the de facto golden gate between a design and a foundry for manufacturing the chip for… Read More


Fast buses at DAC

Fast buses at DAC
by Paul McLellan on 04-24-2012 at 10:05 pm

UPDATE: there is free WiFi on all buses.

OK, these are not the 128 bit 1GHz buses we have to hear about every day. They go roughly 40 miles in roughly an hour. But they take you from Silicon Valley to DAC and back, and they are cheaper than BART or Caltrain.

For the first time this year, DAC has buses from Silicon Valley to Moscone for DAC. … Read More