Cadence TECHTALK: Simulating Fluid-Structure Interaction (FSI) with Fidelity

Cadence TECHTALK: Simulating Fluid-Structure Interaction (FSI) with Fidelity
by Admin on 02-20-2023 at 7:01 pm

Fluid-Structure Interaction (FSI) modeling is a fundamental step in the design process of turbomachinery. Highly variable pressure loads and temperature gradients affect not only efficiency and performance but also the structural integrity of blades.

FSI simulations are a challenging activity where mesh deformation techniques,… Read More


Cadence TECHTALK: Self-Propulsion CFD Simulations: Get Them Right and Fast

Cadence TECHTALK: Self-Propulsion CFD Simulations: Get Them Right and Fast
by Admin on 02-20-2023 at 6:38 pm

Date: Thursday, February 23, 2023

Time: 8:00am PST | 10:00am CST | 5:00pm CET

Cadence helps the maritime industry effectively achieve ship contract speed while respecting the new environmental regulations implemented in 2023. To accomplish this, self-propulsion simulations are crucial and must provide accurate information

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CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff

CadenceTECHTALK: Cadence Certus | Delivering Overnight Concurrent Full-chip Optimization and Signoff
by Admin on 01-16-2023 at 2:15 pm

Date: 2023 .02. 17 (Thursday)

Time: 14:00pm – 15:00pm (Taipei Time)

Wondering how to accelerate your design closure?

The Cadence Certus Closure Solution is the industry’s first fully automated and massively distributed environment for full-chip optimization and signoff. It delivers up to 10X concurrent chip-level

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CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML

CadenceTECHTALK: Find Elusive Bugs Faster with Xcelium ML
by Admin on 01-16-2023 at 2:13 pm

Crack the Verification Double Trouble!

Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.

Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with… Read More


CadenceTECHTALK: Static Timing Analysis and Some Important Basics

CadenceTECHTALK: Static Timing Analysis and Some Important Basics
by Admin on 01-16-2023 at 2:11 pm

Date: Thursday, January 26, 2023

Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST

Static Timing Analysis (STA) aims to validate the timing performance of a synchronous design. While it is a well-known concept in modern digital implementation flows, for engineers who are not familiar with STA or others who would like

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CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation
by Admin on 01-16-2023 at 2:09 pm

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More


CadenceTECHTALK: Integrated Thermal Analysis for RF MMIC and PCB Power Applications

CadenceTECHTALK: Integrated Thermal Analysis for RF MMIC and PCB Power Applications
by Admin on 01-16-2023 at 2:07 pm

Date: Tuesday, January 24, 2023

Time: 09:00 GMT / 10:00 CET / 11:00 EET & Israel / 14:30 IST

Join us for this one-hour CadenceTECHTALK to learn how the Cadence Celsius Thermal Solver uses design data such as layout geometries, material properties, and dissipated power simulation results from Microwave Office software to provide

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Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster

Webinar: Find More Bugs, Hit the Most Difficult Scenarios Faster
by Admin on 12-20-2022 at 12:51 pm

Register for CadenceTECHTALK to find out how to achieve verification closure with the same coverage with up to a 10X reduction in simulation cycles.

Chips are becoming bigger and more complex, adding to already existing verification woes. Design and verification engineers struggle with running billions of regression cycles… Read More


Cadence TECHTALK: LMG Marin Cuts Time and Costs in Ship Design Using Fine Marine

Cadence TECHTALK: LMG Marin Cuts Time and Costs in Ship Design Using Fine Marine
by Admin on 10-19-2022 at 2:49 pm

Date: Thursday, November 10, 2022

Time: 9:00am CDT | 4:00pm CEST

LMG Marin is a naval architecture design and engineering office working on commercial ships, such as ferries, tankers, tugs, and catamarans. The role CFD plays in their processes has grown considerably over the years, and it has replaced towing tank tests in most … Read More


Cadence TECHTALK: Reduce Turnaround Times with an RF/microwave Front-to-Back PCB Workflow

Cadence TECHTALK: Reduce Turnaround Times with an RF/microwave Front-to-Back PCB Workflow
by Admin on 10-19-2022 at 2:31 pm

Date: Thursday, November 10, 2022

Time: 9:00am – 10:00am (PDT)

RF/microwave IP, developed in a specialized design environment, must be transferred to a PCB layout editor where manufacturing constraints, design rule checking (DRC), layout vs. schematic (LVS), and corporate-approved components can be applied and integrated… Read More