RealTime Digital DRC Can Save Time Close to Tapeout

RealTime Digital DRC Can Save Time Close to Tapeout
by Tom Simon on 06-07-2021 at 6:00 am

RealTime DRC

Over the years DRC tools have done an admirable job of keeping pace with the huge growth of IC design size. Yet, DRC runs for sign off on the full design using foundry rule decks take many hours to complete. These long run times are acceptable for final sign off, but there are many situations where DRC results are needed quickly when small… Read More


Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.

Trust, but verify. How to catch peanut butter engineering before it spreads into your system — Part 2: Verification.
by Raul Perez on 02-09-2021 at 10:00 am

iStock 1176843522

This article about verification is part 2 of a two article series. Please see part 1 on validation HERE.

Verification is a field that has emerged as its own discipline. It’s no longer being relegated to an activity led by the design team to which time is allocated as long as it doesn’t get in the way of designing. Chip companiesRead More


Billion Transistor Designs Need Faster Full Chip Tools

Billion Transistor Designs Need Faster Full Chip Tools
by Tom Simon on 06-19-2018 at 12:00 pm

During the design cycle as tape out approaches, time pressure usually goes up dramatically. To make matters worse the design itself is much larger, because all the block level work is done and there is a requirement to work with the entire database. It feels like it’s time to put aside the garden trowel and start using a steam shovel.… Read More