Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward

Building better design flows with tool Open APIs – Calibre RealTime integration shows the way forward
by Peter Bennet on 12-22-2022 at 10:00 am

calibre real time digital and custom

You don’t often hear about the inner workings of EDA tools and flows – the marketing guys much prefer telling us about all the exciting things their tools can do rather than the internal plumbing. But this matters for making design flows – and building these has largely been left to the users to sort out. That’s an increasing challenge… Read More


WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs

WEBINAR: Intel Achieving the Best Verifiable QoR using Formal Equivalence Verification for PPA-Centric Designs
by Synopsys on 08-30-2022 at 10:00 am

Synopsys Fusion Compiler

Synopsys Fusion Compiler offers advanced optimizations to achieve the best PPA (power, performance, area) on today’s high-performance cores and interconnect designs. However, advanced transformation techniques available in synthesis such as retiming, multi-bit registers, advanced datapath optimizations, etc. are

Read More

Useful Skew in Production Flows

Useful Skew in Production Flows
by Tom Dillinger on 12-13-2019 at 6:00 am

The concept of applying useful clock skew to the design of synchronous systems is not new.  To date, the application of this design technique has been somewhat limited, as the related methodologies have been rather ad hoc, to be discussed shortly.  More recently, the ability to leverage useful skew has seen a major improvement,… Read More