Ex ante: disclose IP before, not after standardization

Ex ante: disclose IP before, not after standardization
by Don Dingee on 08-17-2012 at 3:46 pm

Many of the audience here are involved in standards bodies and specification development, so the news from the Apple v. Samsung on the invocation of ex ante in today’s testimony is useful.

I worked with VITA, the folks behind the VME family of board-level embedded technology, on their ex ante policy several years ago, and … Read More


View from the top: Ajoy Bose

View from the top: Ajoy Bose
by Paul McLellan on 12-12-2011 at 4:13 pm

I sat down yesterday with Dr. Ajoy Bose, CEO of Atrenta, to get his view of the future of EDA – looking through a high-power “spyglass” of sorts. I first met Ajoy when he was at Software & Technologies. I was then the VP of Engineering for Compass Design Automation and we were considering off-shoring some development. We eventually… Read More


Interoperability Forum

Interoperability Forum
by Paul McLellan on 12-03-2011 at 3:19 pm


Earlier this week I went to the Synopsys Interoperability Forum. The big news of the day turned out to be Synopsys wanting to be more than interoperable with Magma, but that only got announced after we’d all gone away.

Philippe Margashack of ST opened, reviewing his slides from a presentation at the same forum from 10 years … Read More


EDA Interoperability Forum

EDA Interoperability Forum
by Paul McLellan on 11-09-2011 at 3:06 pm

The 24th Interoperability Forum is coming up at the end of the month on November 30th to be held at the Synopsys compus in Mountain View. It lasts from 9am until lunch (and yes, Virginia, there is such a thing as a free lunch). I think it looks like a very interesting way to spend a morning.

Here are the speakers and what they are speaking… Read More


Analog Constraint Standards

Analog Constraint Standards
by Paul McLellan on 09-20-2011 at 8:00 am

Over the years there has been a lot of standard creation in the IC design world to allow interoperability of tools from different vendors. One area of recent interest is interoperable constraints for custom IC design. Increasingly, analog design layout is becoming more automated. Advanced process nodes require trial layouts… Read More