Power Integrity Challenges for High Speed and High Frequency Designs

Power Integrity Challenges for High Speed and High Frequency Designs
by Daniel Nenni on 10-14-2012 at 8:30 pm

There is an interesting discussion on the LinkedIn SoC Power Integrity Group in regards to the power integrity challenges for high speed and high frequency designs. More specifically, the additional attention an on-chip power delivery network (PDN) requires as the operating frequency of ICs and SoCs increases.

The PDN has to… Read More