Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification

Webinar: Reduce Gate-level Simulation Bring-up Time with Semi-formal X Verification
by Admin on 03-07-2024 at 3:13 pm

Gate-level simulations (GLS) are a crucial step in the verification of an ASIC/FPGA. GLS is used for verifying power-up, reset operation, timing, multi-cycle paths, and power estimation. However, GLS can be a bottleneck in the project cycle due to its complexity. The nature of a GLS can cause simulations to run much longer than

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