Join this webinar and see UCIe in action! This webinar presents the SystemVerilog models of a Universal Chiplet Interconnect Express (UCIe) interface, including both the analog circuits in the electrical layer and digital FSMs in the logical layer. The whole physical layer (PHY) model can be efficiently simulated in SystemVerilog,… Read More
Webinar: Modeling and Simulation of Silicon Photonics Systems in SystemVerilog
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Silicon photonics systems integrate photonic components such as optical waveguides, couplers, resonators, photodetectors, etc. along with electronic components on the same silicon chip to realize high-bandwidth, high-density, and low-power communication via wavelength-division multiplexing (WDM). This talk… Read More