Beyond DRC and LVS, why Reliability Verification is used by Foundries

Beyond DRC and LVS, why Reliability Verification is used by Foundries
by Daniel Payne on 09-18-2018 at 12:00 pm

Reliability of ICs isn’t a new thing, because back in 1980 I was investigating why a DRAM chip using 6um technology was having yield loss due to electromigration effects. I recall looking through a microscope at a DRAM layout and slowly ramping up the Vdd level then suddenly the shiny aluminum interconnect started to change… Read More