How About a Quality-Aware IP Design Flow

How About a Quality-Aware IP Design Flow
by Daniel Payne on 05-28-2014 at 6:18 pm

In the EDA world we use hyphens quite often to describe our technical approaches, like: DFM-aware, Power-aware, Variation-aware. I just read a white papertoday on the topic of Quality-Aware IP Design Flows, written by Fractal Technologies. If your group creates IP or re-uses IP, then there’s always the question about … Read More


Not me. Who owns IP quality?

Not me. Who owns IP quality?
by Paul McLellan on 03-05-2012 at 4:32 pm

Now that the dominant approach to building an SoC is to get IP from a number of sources and assemble it into a chip, the issue of IP quality is more and more critical. A chip won’t work if the IP doesn’t work, but it is quite difficult to verify this because the SoC design team is not intimately familiar with the IP blocks since… Read More


Atrenta/TSMC Soft-IP Alliance: 10 companies make the grade

Atrenta/TSMC Soft-IP Alliance: 10 companies make the grade
by Paul McLellan on 03-05-2012 at 7:30 am

Last May, Atrenta and TSMC announced the Soft-IP Alliance Program which uses SpyGlass and a subset of its GuideWare reference methodology to implement TSMC’s IP quality assessment program. TSMC requires all soft-IP providers to reach a minimum level of completeness before their IP is listed on TSMC online. Since TSMC … Read More


How Good is Your Verification?

How Good is Your Verification?
by Paul McLellan on 05-11-2011 at 5:00 am

The traditional way for analyzing the effectiveness of testing in the software world and in the RTL world is code coverage. Make sure that every line of code is executed. This is a pretty crude measure since even 100% code coverage doesn’t mean that all the condition has really been tested but it is certainly necessary–after… Read More