One of the most promising advancements in the semiconductor field is the development of 3D Integrated Circuits (3D ICs). 3D ICs enable companies to partition semiconductor designs and seamlessly integrate silicon Intellectual Property (IP) at the most suitable process nodes and processes. This strategic partitioning yields… Read More
Tag: parasitics
Balancing analog layout parasitics in MOSFET differential pairs
The MOSFET differential pair is a key part of many analog circuits e.g. opamps, comparators, LDOs, etc. A differential pair applies gain to the difference between two signals and has many advantages over single-ended amplifier circuits, e.g. noise reduction and suppression of common-mode signals and DC offset. However, these
Effect of Inductance on Interconnect
In previous design generations interconnect could safely be modeled by extraction using just R and C values. Parasitics in interconnect are important because they can affect the operating frequency or phase error in circuits like VCO’s. The need to model parasitics properly in wires is just as applicable in PA’s, LNA’s and for… Read More