Tag: paradigm

IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis

IR 2.0 – Building a New Paradigm for Power Integrity Design and Analysis
by Admin on 10-25-2023 at 3:53 pm

Date: November 2, 2023

Time: 10:00am – 5:00pm

Location: Cadence Headquarters, San Jose, CA | Building 5 – Big Sur

Power integrity (PI) is a major challenge for chip designers in the era of ubiquitous data, hyperconnectivity, and AI. Design size is exploding, and innovations in heterogenous integration are adding to PI complexity.

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