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A random walk down OS-VVMby Don Dingee on 05-13-2013 at 11:14 amCategories: Aldec, EDA
Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer… Read More
How many languages an Engineer should speak?by ahmed.shahein on 06-08-2012 at 9:37 amCategories: EDA
I speak VHDL and SystemC, others speak Verilog and SystemVerilog … what do you speak?
Before getting into the core of the topic let me give you some round figures, engineers love numbers. Julian Lonsdale “European Sales Manager at Aldec” informed me at the Xfest Munich last month that Aldec carried out a survey to evaluate the usage… Read More
