Tag: osvvm

DVClub Europe: Latest VHDL Verification Techniques

DVClub Europe: Latest VHDL Verification Techniques
by Admin on 02-26-2024 at 8:01 pm

DVClub Europe: Latest VHDL Verification Techniques

This DVClub focuses on the latest verification techniques in VHDL including UVVM and OSVVM

Agenda (GMT)

13:00 Welcome and Introduction – Mike Bartley, Tessolve

13:00 Espen Tallaksen, EmLogic – Get the right FPGA quality through efficient Specification Coverage… Read More

Advances in OSVVM’s Verification Data Structures (US)

Advances in OSVVM’s Verification Data Structures (US)
by Admin on 06-22-2022 at 1:20 pm

Abstract:

OSVVM has grown tremendously over the last couple of years. This period saw simulator independent scripting, test reporting, model independent transactions, virtual transaction interfaces, and additional verification components, each added and incrementally improved. We have talked about these previously

… Read More

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM

Better FPGA Verification with VHDL – Faster than “Lite” Verification Component Development with OSVVM
by Admin on 06-08-2022 at 2:50 pm

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

Part 2: Faster than “Lite” Verification Component Development with OSVVM (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, June 9, 2022

11:00 AM – 12:00 PM (PDT)… Read More

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)

LIVE WEBINAR: Better FPGA Verification with VHDL (Four Part Webinar Series)
by Admin on 05-18-2022 at 4:35 pm

Part 1: OSVVM – Leading Edge Verification for the VHDL Community (US)

Jim Lewis, VHDL User, Designer, Verification Engineer, Trainer, OSVVM developer, and IEEE VHDL Chair

Thursday, May 26, 2022

11:00 AM – 12:00 PM (PDT)

Abstract:

OSVVM is an advanced verification methodology that defines a VHDL verification framework,

… Read More
Posted on

A random walk down OS-VVM

A random walk down OS-VVM
by Don Dingee on 05-13-2013 at 11:14 am
Categories: Aldec, EDA

Unlike one prevailing theory of financial markets, digital designs definitely don’t function or evolve randomly. But many engineers have bought into the theory that designs can be completely tested randomly. Certainly there is value to randomness, exercising all combinations of inputs, including unexpected ones a designer… Read More

Posted on

How many languages an Engineer should speak?

How many languages an Engineer should speak?
by ahmed.shahein on 06-08-2012 at 9:37 am
Categories: EDA
19 Comments

I speak VHDL and SystemC, others speak Verilog and SystemVerilog … what do you speak?

Before getting into the core of the topic let me give you some round figures, engineers love numbers. Julian Lonsdale “European Sales Manager at Aldec” informed me at the Xfest Munich last month that Aldec carried out a survey to evaluate the usage… Read More