I wrote last month about physically aware NoC design, so you shouldn’t be surprised that Arteris is now offering exactly that capability 😊. First, a quick recap on why physical awareness is important, especially below 16nm. Today, between the top level and subsystems a state-of-art SoC may contain anywhere from five to twenty … Read More
Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design. Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and… Read More
Dan is joined by Dr. Giovanni De Micheli, a research scientist in electronics and computer science credited with inventing the network-on-chip (NoC) design automation paradigm and creating EDA algorithms and design tools. Before serving as Professor and Director of the Integrated Systems Laboratory at EPFL, he was Professor… Read More
