In Low Voltage Timing, the Center Cannot Hold

In Low Voltage Timing, the Center Cannot Hold
by Bernard Murphy on 01-25-2016 at 7:00 am

When I started discussing this topic with Isadore Katz, I was struggling to find a simple way to Image Removedexplain what he was telling me – that delay and variance calculations in STA tools are wrong at low voltage because the average (the center) of a timing distribution shifts from where you think it is going to be. He told me that… Read More


Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?

Ultra-low Voltage: Is Your Slack Really Positive? Are You Sure?
by Paul McLellan on 08-06-2015 at 7:00 am

Image RemovedDuring synthesis and static timing the main figure of merit is “slack”. If a signal arrives with time to spare before it is needed (often measured against the setup time before a clock changes at a register) then the slack is positive. Positive slack is generally a good thing, although it can indicate over-design… Read More


Voltage Limbo Dancing: How Low Can You Go?

Voltage Limbo Dancing: How Low Can You Go?
by Paul McLellan on 03-09-2015 at 7:00 am

Image RemovedAll chips these days have to worry about power. Indeed it is typically the top of the priority list of concerns, above performance and even area. Transistors are effectively fast and free, but you can’t have too many of them (at least turned on at once). The most obvious way to reduce power is to lower the supply … Read More