Hello Cambridge, Grenoble, Stockholm, Moscow, Munich and Amsterdam
Our 2019 global symposiums and workshops have been hugely successful in promoting the RISC-V ISA and fostering expansive collaboration within the open-source community. It’s invigorating to see how the worldwide semiconductor ecosystem is energized and… Read More
Tag: krste asanovic
The Revolution Evolution Continues – SiFive RISC-V Technology Symposium – Part II
During the afternoon session of the Symposium, Jack Kang, SiFive VP sales then addressed the RISC-V Core IP for vertical markets from consumer/smart home/wearables to storage/networking/5G to ML/edge. Embedding intelligence from the edge to the cloud can occur with U Cores 64-bit Application Processors, S Cores 64-bit Embedded… Read More
The Dawn of a New RISC
The 8[SUP]th[/SUP] RISC-V Workshop was held in Barcelona May 7-10 with 325 attendees from 150+ companies and was the biggest RISC-V event outside of Silicon Valley, demonstrating the momentum of the RISC-V Foundation and the growth of the ecosystem in Europe.… Read More
Getting Started with RISC-V
As I mentioned before, SiFive and RISC-V are trending topics on SemiWiki.com which makes complete sense since we have been covering semiconductor IP and ARM since we first went online in January of 2011.
In total we have published 707 IP related blogs that earned 3,565,140 views (5043 views per blog average). Out of that, 254 are … Read More