The most common way to evaluate a power distribution network is to look at its impedance over the effective frequency range. A lower impedance will produce less noise when transient current is demanded by the IC output buffers. However, this transient current needs to be provided at the same time for each transition or jitter will… Read More
In this episode of the Semiconductor Insiders video series, Dan is joined by Samia Rashid, co-founder and president of Infinisim. Samia provides detailed background on clock jitter – what it is, what causes it and the various methods to address the problem. Samia describes the unique clock analysis technology developed… Read More
PCB designers can perform pre-route simulations, follow layout and routing rules, hope for the best from their prototype fab, and yet design errors cause respins which delays the project schedule. Just because post-route analysis is time consuming doesn’t mean that it should be avoided. Serial links are found in many PCB designs,… Read More
