Defacto Technologies and ARM, Joint SoC Flow at #61DAC

Defacto Technologies and ARM, Joint SoC Flow at #61DAC
by Daniel Payne on 07-31-2024 at 10:00 am

arm defacto 61dac min

At #61DAC I stopped by the Defacto Technologies exhibit and talked with Chouki Aktouf, President and CEO, to find out what’s new in 2024. ARM and Defacto have a joint SoC design flow by using the Arm IP Explorer tool along with Defacto’s SoC compiler, which helps to quickly create your top-level RTL, IP-XACT and UPF files. This tool… Read More


A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC

A Joint Solution Toward SoC Design “Exploration and Integration” released by Defacto #61DAC
by Daniel Nenni on 07-23-2024 at 6:00 am

flow ip explorer soc compiler (1)

When I was at DAC last month, I had the chance to talk with Chouki Aktouf and Bastien Gratréaux from Defacto and they told me about a new innovative solution to generate Arm-based System-on-Chips. I heard that this solution has now been released.

Defacto and Arm developed a joint SoC design flow to help Arm users cover all needed automation—from… Read More


Defacto at the 2024 Design Automation Conference

Defacto at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 10:00 am

DAC 2024 Banner

Defacto continues to confirm its SoC Compiler as becoming the “de facto” SoC integration solution for large SoC designs. This year they are coming to DAC to share customer success stories of building the largest SoCs in the market from specification to RTL + collaterals such as UPF by including thousands of IP cores! All done within… Read More


Arteris is Solving SoC Integration Challenges

Arteris is Solving SoC Integration Challenges
by Mike Gianfagna on 06-06-2024 at 6:00 am

Arteris is Solving SoC Integration Challenges

The difficulty of SoC integration is clearly getting more demanding. Driven by process node density, multi-chip integration and seemingly never-ending demands for more performance at lower power, the hurdles continue to increase. When you consider these challenges in the context of Arteris, it’s natural to think about hardware… Read More


When Will Structured Assembly Cross the Chasm?

When Will Structured Assembly Cross the Chasm?
by Bernard Murphy on 12-13-2023 at 6:00 am

Trends in assembly min

First, a quick definition. By “structured assembly,” I mean the collection of tools to support IP packaging with standardized interfaces, SoC integration based on those IPs together with bus fabric and other connectivity hookups, register definition and management in support of hardware/software interface definition, Read More


An Update on IP-XACT standard 2022

An Update on IP-XACT standard 2022
by Daniel Payne on 10-18-2023 at 10:00 am

IP XACT 2022 min

Semiconductor IP design re-use has enabled the relentless growth in complexity of SoC and chiplet-based systems over the years, and with IP reuse comes many unique challenges.  Fabless design companies use IP provided by a vibrant ecosystem of IP suppliers and foundries, plus internal re-use in the quest to get to market more … Read More


Defacto Celebrates 20th Anniversary @ DAC 2023!

Defacto Celebrates 20th Anniversary @ DAC 2023!
by Daniel Nenni on 07-05-2023 at 10:00 am

20ans signature clean

Defacto Technologies is a company that specializes in Electronic Design Automation (EDA) software and solutions. Defacto offers a range of EDA software solutions that help streamline and optimize various stages of the front-end design process. Their tools focus on chip design assembly and integration before logic synthesis

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Podcast EP137: The International Impact of Accellera’s Work

Podcast EP137: The International Impact of Accellera’s Work
by Daniel Nenni on 01-13-2023 at 10:00 am

Dan is joined by Lu Dai who is currently a Senior Director of Technical Standards at Qualcomm. Previously he was Senior Director of Engineering, leading Qualcomm’s SoC design verification team and front-end methodologies and initiatives. Lu is Chair of Accellera Systems Initiative and serves on the Board of Directors at RISC-V… Read More


STOP Writing RTL for Registers

STOP Writing RTL for Registers
by Steve Walters on 10-17-2022 at 6:00 am

Semifore EDA Software

After almost three decades in the EDA business, it is beyond my comprehension to understand why chip designers still hand-write RTL for complex register maps – chip designs with hundreds of registers and thousands of register fields.  In today’s silicon world where software is the key to chip-based product success, it is the register… Read More


Jade Design Automation’s Register Management Tool

Jade Design Automation’s Register Management Tool
by Kalar Rajendiran on 07-05-2022 at 10:00 am

RegMan supervisor CSRs

When more than one person is working on any project, coordination is imperative. When the team size grows, being in sync becomes essential. When it comes to SoC design management, registers and bit fields are used to communicate status of results and execute conditional controls. The Register Management function plays an essential… Read More