While FinFET yield controversy is going on, I see a lot being done to improve that yield by various means. One prime trend today, it must be, it’s worthwhile, is to pull up various signoffs as early as possible during the design cycle. And DFM signoff is a must with respect to yield of fabrication. This reminds me about my patents filed… Read More
CadenceTECHTALK: In-Design EM Analysis Addresses RF System Integration Challenges
Date: Tuesday, September 20, 2022
Time: 10:00am PDT / 1:00pm EDT
The RF PA MMIC worked as designed until it was integrated into the module housing, and then the overall performance shifted out of spec. Design failure at the point of system integration is a common cause of delayed product deliveries and engineering cost overruns.… Read More