Tag: in-design

Cadence TechTalk: Design Robust IC Packages Faster Using In-Design SI/PI Analysis

Cadence TechTalk: Design Robust IC Packages Faster Using In-Design SI/PI Analysis
by Admin on 04-17-2023 at 3:30 pm

IC package design teams and characterization teams have had a “throw-it-over-the-wall” relationship for decades, which often delays design releases by months. However, as signal integrity (SI) and power integrity (PI) challenges evolve with multi-die heterogeneous integration, the need to perform SI/PI analysis as part

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CadenceTECHTALK: In-Design EM Analysis Addresses RF System Integration Challenges

CadenceTECHTALK: In-Design EM Analysis Addresses RF System Integration Challenges
by Admin on 09-15-2022 at 1:53 pm

Date: Tuesday, September 20, 2022

Time: 10:00am PDT / 1:00pm EDT

The RF PA MMIC worked as designed until it was integrated into the module housing, and then the overall performance shifted out of spec. Design failure at the point of system integration is a common cause of delayed product deliveries and engineering cost overruns.… Read More

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In-Design DFM Signoff for 14nm FinFET Designs

In-Design DFM Signoff for 14nm FinFET Designs
by Pawan Fangaria on 11-04-2014 at 4:00 pm
Categories: Cadence, EDA, Foundries

While FinFET yield controversy is going on, I see a lot being done to improve that yield by various means. One prime trend today, it must be, it’s worthwhile, is to pull up various signoffs as early as possible during the design cycle. And DFM signoff is a must with respect to yield of fabrication. This reminds me about my patents filed… Read More