Synopsys IC Validator at DAC

Synopsys IC Validator at DAC
by Daniel Payne on 06-14-2011 at 3:14 pm

At DAC last week I visited the Synopsys demo suite to see what’s new with IC Validator.

Stelios Diamantidis, PMM
– In-design physical verification
– Sign-off reveals thousands of late stage DRC violations
– 28nm has 1.5K rules, 15K runset sizes
– Metal Fill changes timing
– The… Read More