How Arteris is Revolutionizing SoC Design with Smart NoC IP

How Arteris is Revolutionizing SoC Design with Smart NoC IP
by Mike Gianfagna on 05-12-2025 at 6:00 am

How Arteris is Revolutionizing SoC Design with Smart NoC IP

Recently, Design & Reuse held its IP-SoC Days event at the Hyatt Regency in Santa Clara. Advanced IP drives a lot of the innovation we are seeing in chip design. This event provides a venue for IP providers to highlight the latest products and services and share a vision of the future. IP consumers are anxious to hear about all the… Read More


Smart Clock Gating for Meaningful Power Saving

Smart Clock Gating for Meaningful Power Saving
by Pawan Fangaria on 01-21-2014 at 5:30 am

Since power has acquired a prime spot in SoCs catering to smart electronics performing multiple jobs at highest speed; the semiconductor design community is hard pressed to find various avenues to reduce power consumption without affecting functionality and performance. And most of the chips are driven by multiple clocks that… Read More