Our previous Blue Pearl post looked at the breadth of contextual visualization capability in the GUI to speed up debug. Two other important aspects of the ASIC & FPGA pre-synthesis workflow are automating analysis with scripts and managing the stream of messages produced. Let’s look at these aspects… Read More
Static low-power verification enables engineers to verify and debug multimillion-gate designs optimized for low power, without complex and time-consuming simulations. However, understanding these IEEE 1801 violations and diagnosing the root cause can become challenging without a user-friendly debug infrastructure.