Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores

Webinar: A Novel Approach to Implementing Logical ECOs with Synopsys Formality ECO on High Performance RISC-V Cores
by Admin on 07-13-2023 at 9:27 pm

Wednesday, July 26, 2023 | 10:00 a.m. – 11:00 a.m. PDT

RTL engineering change order (ECO) is vital to ensuring proper functionality of integrated circuits (ICs). Retiming and auto ungrouping optimize RTL implementation and enhance PPA. However, aggressive optimizations in CPU RTL designs present challenges due to increased

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Webinar: Achieving Fast Turnaround Time of Functional ECOs with Synopsys Formality ECO

Webinar: Achieving Fast Turnaround Time of Functional ECOs with Synopsys Formality ECO
by Admin on 09-27-2022 at 9:53 pm

Synopsys Webinar | Thursday, November 9, 2022 | 10 a.m. Pacific

Functional ECOs (engineering change orders) are an important part of the design cycle, enabling design teams to respond quickly to frequent, unexpected, and last-minute register-transfer logic (RTL) functional changes. ECOs are unavoidable, however,

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